Director of Digital Design Engineering, Memory Interface IP

Category Engineering Hire Type Employee Job ID 18571 Remote Eligible No Date Posted 09/13/2026

Job Title

• Director of Digital Design Engineering, Memory Interface IP

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the world of high-speed memory interfaces, where timing closure is measured in picoseconds and a single protocol violation can sink a tape-out. You know HBM, DDR, and LPDDR not as acronyms but as living systems with tradeoffs you have navigated across multiple generations. Leading a design team is not about holding status meetings. It is about knowing when to step into a critical path issue at 4 p.m. on a Friday and when to let your engineers own the solution. You have built teams that ship, and you know the difference between a group that executes and one that just stays busy.

You do not manage from a distance. You review RTL, you ask the hard questions during design reviews, and you push back when a verification plan is too thin or a schedule is built on hope. At the same time, you trust your people, you clear obstacles, and you create space for them to do their best work. You have worked with executive stakeholders and you can translate a technical risk into a business decision without losing the engineering substance. At Synopsys, you will lead a team building memory interface IP that powers the next wave of AI and high-performance compute.

What You'll Be Doing

• Lead a team of ASIC digital design and verification engineers working on HBM, DDR, and LPDDR memory interface IP
• Own the technical direction and execution of RTL design and verification at both block and chip integration levels
• Drive design reviews, architecture decisions, and quality checkpoints across the full development cycle from spec to silicon
• Collaborate with cross-functional teams including analog design, DFT, physical design, and product management to align on specifications, schedules, and deliverables
• Build and refine design and verification methodologies, incorporating AI-driven tools and automation to improve efficiency and quality
• Manage project timelines, resource allocation, and risk mitigation to deliver on schedule and within scope
• Mentor and develop engineers, providing technical guidance and career growth opportunities across the team

The Impact You Will Have

• Deliver memory interface IP that enables the next generation of AI accelerators, data center processors, and high-performance SoCs
• Raise the bar for design quality and verification coverage across one of the most performance-critical IP domains in the industry
• Shape the technical roadmap for high-speed memory controllers that will be integrated into products shipping at scale
• Build a high-performing team culture where engineers grow, ship complex designs, and solve hard problems together
• Accelerate time to market by driving adoption of advanced methodologies, automation, and AI-assisted design flows
• Strengthen Synopsys' leadership position in memory interface IP by delivering differentiated, production-proven solutions
• Influence product strategy and customer engagements through deep technical insight and execution credibility

What You'll Need

• 15 - 20+ years of experience in ASIC digital design and verification, with significant hands-on work in memory interface IP such as HBM, DDR, or LPDDR
• Proven track record leading engineering teams through full product development cycles from architecture to silicon bring-up
• Deep expertise in RTL design, verification methodologies, and design closure for high-speed digital interfaces
• Strong understanding of memory protocols, PHY/controller architecture, signal integrity, and timing closure challenges
• Experience managing cross-functional collaboration with analog, physical design, and product teams
• Demonstrated ability to communicate technical risks, tradeoffs, and project status to executive leadership and stakeholders
• Experience with AI-driven design tools or a strong interest in integrating AI into design and verification flows is a plus

Who You Are

• You can walk into a design review, spot the gap in a verification plan or a timing assumption, and ask the question that changes the outcome
• You build teams that want to work for you because you clear the path, give honest feedback, and celebrate the wins that matter
• You are comfortable making hard calls under uncertainty, whether it is a schedule tradeoff, a resource decision, or a technical pivot
• You do not wait for perfect information to act, you gather what you need, align the right people, and move forward with clarity
• You care about the details but you do not micromanage, you know when to zoom in and when to let your engineers own the problem
• You see AI not as a buzzword but as a practical tool to improve design quality, automate repetitive work, and accelerate decision-making

The Team You'll Be Part Of

You will be joining a highly skilled and motivated team of ASIC Digital Design engineers. Our team is dedicated to pushing the boundaries of technology and delivering groundbreaking solutions. We value collaboration, continuous learning, and we are looking for someone who shares our commitment to excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.