Layout Design, Staff Engineer

Category Engineering Hire Type Employee Job ID 19598 Remote Eligible No Date Posted 11/03/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of custom layout, working on designs where a 10-micron mistake costs months and where matching, symmetry, and parasitic control are not nice-to-haves but the entire point. You know that a great floorplan is not about fitting everything in, it is about making the right tradeoffs between area, routing congestion, and signal integrity before anyone writes a single polygon. You have debugged EMIR violations at 3am and walked out knowing exactly which power stripe needed to move and why.

You do not just execute layouts, you think about them. When someone hands you a schematic, you are already mentally placing critical pairs, planning guard rings, and asking about the ESD strategy. You have worked in 7nm or below, and you understand that FinFET and GAA are not just smaller nodes, they are different games with different rules. You mentor without micromanaging, you lead without needing the title, and you care about the quality of what ships, not just what closes timing.

At Synopsys, you will work on DDR and HBM PHY IP that powers the memory subsystems in everything from data centers to AI accelerators. The work is hard, the standards are high, and the team expects you to bring both hands and brain.

What You'll Be Doing

• Lead layout development for next-generation DDR and HBM PHY IP across 7nm, 5nm, and below in FinFET and GAA process technologies
• Own floorplanning, layout execution, and design reviews for critical analog and mixed-signal blocks within memory PHY subsystems
• Drive layout quality through PERC, EMIR, DFM checks, LEF generation, and release readiness, ensuring designs meet foundry and customer specifications
• Collaborate with circuit design, verification, and product engineering teams to resolve layout-related issues, optimize for area and performance, and meet project schedules
• Mentor junior layout engineers on matching techniques, ESD and latch-up strategies, IO frame requirements, and deep submicron layout best practices
• Estimate effort, plan schedules, and execute layout deliverables in cross-functional project settings with accountability for timelines and quality
• Support customer-specific PHY requirements including bond-pad layout, pitch constraints, and custom IO configurations

The Impact You Will Have

• Enable Synopsys customers to integrate high-performance, low-power memory subsystems into SoCs powering AI, 5G, automotive, and cloud applications
• Accelerate time-to-market for next-generation DDR and HBM IP by delivering layout that works the first time and scales across process nodes
• Raise the technical bar for the layout team through hands-on mentorship, design reviews, and shared best practices that improve quality and efficiency
• Reduce design respins and foundry-related issues by catching deep submicron effects, parasitic mismatches, and DFM violations early in the layout cycle
• Strengthen cross-functional collaboration between layout, circuit design, and product teams, ensuring alignment on requirements, schedules, and tradeoffs
• Build reusable layout methodologies and IP blocks that scale across future memory PHY products and process technologies
• Contribute to Synopsys Silicon IP's reputation for delivering world-class, production-proven memory interface solutions

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, VLSI Design, or related field
• 5+ years of hands-on custom layout experience, with demonstrated leadership on complex analog or mixed-signal IP projects
• Deep expertise in layout for 7nm and below process nodes, including FinFET and GAA technologies, with strong understanding of deep submicron effects
• Proficiency in layout matching techniques, ESD and latch-up design, PERC, EMIR analysis, DFM checks, and LEF generation
• Experience with PHY-level IP development, including bond-pad layout, IO frame design, and customer pitch requirements
• Proven ability to lead projects, estimate effort, plan schedules, and deliver high-quality layout on time in cross-functional settings
• Experience with DDR, HBM, or high-speed memory interface IP is a strong plus

Who You Are

• You can look at a floorplan and immediately spot the congestion bottleneck or the block that is going to cause EMIR headaches three months from now
• You explain layout tradeoffs to circuit designers and product managers in terms they understand, without losing the technical nuance that actually matters
• You hold yourself and your team accountable for quality, you do not sign off on a layout until you have personally reviewed the critical nets and matching structures
• You mentor by doing, not just telling, juniors learn more from watching you debug a DRC violation than from any presentation slide
• You stay current on foundry rules, process updates, and layout techniques because you know that what worked at 16nm does not always work at 5nm
• You work across geographies and time zones without friction, you respond clearly, you follow through, and you keep the project moving

The Team You'll Be Part Of

You will join the Silicon IP organization within Synopsys, specifically the team developing next-generation DDR and HBM PHY IP. This is a cross-functional team working across layout, circuit design, verification, and product engineering to deliver memory interface solutions that ship in high-volume SoCs worldwide. The team operates globally, and you will collaborate with engineers across geographies to meet aggressive schedules and customer requirements.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.