Alternate Job Titles

• Staff Verification Applications Engineer
• Senior Applications Engineer, Simulation & Debug
• Staff Field Applications Engineer, Verification
• Technical Applications Engineer, VCS/Verdi
• Staff Customer Solutions Engineer, Verification

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the verification trenches and learned that the hardest part is not running the simulation, it is making sure the customer's entire flow actually works when the design is real, the schedules are tight, and the stakes are first-pass silicon. You know the difference between a tool that demos well and one that holds up under a million-gate SoC with Low Power intent and Gate Level Timing checks enabled. You have debugged enough waveforms to spot the issue in minutes, not hours, and you can explain what went wrong to an engineer in Taiwan and an R&D lead in Mountain View without losing either of them.

You do not wait for perfect documentation. You dig into the problem, write the Tcl script that reproduces it, and work backward from there. You are comfortable sitting with a customer who is frustrated because their regression is failing and walking out with a plan that gets them unblocked by end of week. You have a point of view on what makes a verification flow robust, and you are not afraid to push back when a deployment plan skips the hard questions. At Synopsys, you will work directly with customers running the most complex verification challenges in the industry, and what you solve will determine whether their tape-out happens on time.

What You'll Be Doing

• Drive customer deployments of VCS and Verdi simulation and debug technology, working directly with design and verification teams to integrate tools into their existing flows
• Diagnose and resolve complex technical issues across UVM testbenches, SVA assertions, Low Power UPF flows, and Gate Level Timing simulations
• Collaborate with global R&D and product teams to gather customer requirements, reproduce issues, and influence the product roadmap based on real deployment feedback
• Lead competitive engagements by running benchmarks, demonstrating VCS/Verdi advantages, and helping customers evaluate simulation performance and debug efficiency
• Develop and optimize automation scripts in Perl, Tcl, Python, Shell, and Make to improve customer productivity and streamline verification workflows
• Interface directly with customers, product validation teams, and R&D to propose solutions, suggest product improvements, and close the loop on deployment challenges
• Support customers adopting AI-driven verification productivity tools and advanced simulation features as part of their methodology evolution

The Impact You Will Have

• Enable customers to close verification faster and hit first-pass silicon by deploying simulation technology that actually scales to their design complexity
• Reduce time-to-tapeout for semiconductor companies building everything from mobile SoCs to automotive safety-critical designs
• Shape the VCS and Verdi product roadmap by surfacing real customer pain points and competitive gaps that R&D needs to address
• Drive adoption of advanced verification methodologies including UVM, Low Power, and Gate Level Timing simulation across global customer accounts
• Build long-term customer relationships that turn Synopsys tools into the backbone of their verification infrastructure
• Accelerate the industry's shift toward AI-augmented verification by helping customers integrate and adopt new productivity capabilities
• Strengthen Synopsys' competitive position in simulation and debug by winning benchmarks and proving performance in head-to-head evaluations

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering or related field with 5-12 years of hands-on experience in verification or applications engineering
• Strong working knowledge of VCS simulation technology and Verdi debug platform, or equivalent simulation and waveform debug tools
• Deep expertise in SystemVerilog, UVM, SVA, and verification methodologies applied to real RTL designs
• Proven experience with Low Power UPF flows and Gate Level Timing simulations in customer or product validation environments
• Advanced scripting ability in Perl, Tcl, Python, Shell, and Make for automation and flow development
• Solid understanding of digital design fundamentals, Verilog, VHDL, and UNIX/Linux environments
• Exposure to DPI, C/C++, SystemC, Functional Safety, or GenAI technologies is a plus

Who You Are

• You can explain a complex UVM sequence issue to a customer in two sentences and then write the 50-line reproducer that proves it
• Comfortable working across time zones with customers in Asia, Europe, and the US without losing momentum on open issues
• You manage multiple customer engagements at once, keeping track of what is blocking each one and what needs to escalate to R&D
• Self-directed enough to own a customer deployment from kickoff through production without waiting for someone to tell you what to do next
• You ask the questions that uncover the real problem, not just the symptoms the customer described in the ticket
• Open to travel for onsite customer engagements, competitive benchmarks, and team collaboration when it moves the work forward

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.