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ASIC Physical Design, Staff Engineer

Kanata, Ontario, Canada
Engineering
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Overview

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

ASIC Physical Design Engineer, Staff
Seeking a highly motivated and innovative Physical Design Implementation Engineer for the Test Chip PHY team.
Does this sound like a good role for you?

The candidate will lead a team of engineers to develop a Test Chip PHY IP for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with focus on digital design.

Tasks will include but not be limited to, RTL synthesis, creating floor plans, running Place & Route/CTS flows using Synopsys tools, checking design equivalency, performing Static Timing Analysis and timing closure ECOs, constraints development, static and dynamic IR drop analysis, power estimation, electromigration checks and other verifying the test-chips for DRC/LVS/ERC/PERC checks.

Additional tasks will include creation of views necessary for Test Chip tapeout, conducting mock tapeouts and running all required QA checks before release of these views. The candidate will work independently to find solutions to complex design implementation issues and to suggest improvements to the design methodology and design flows

Key Requirements

  • Requires a degree in Electrical/Electronics Engineering (or equivalent) and 8+ years working experience in a related field.
  • Previous experience of leading a project as Technical Lead.
  • Previous experience with Physical Design of SOCs or IPs with ability to handle broad responsibility from RTL to signoff of Digital ASIC Test Chip designs.
  • Prior knowledge and experience with state-of-the-art CAD tools (DC, PT, ICC2/FC, ICV) and technologies (FinFet) is required. 
  • Previous experience of working on RTL synthesis, SDCs and timing signoff using PTSI, RDL, Bump Map integration, ESD, Chip finishing is required.
  • Experience with solving Physical Verification (DRC, LVS, Antenna, etc) violations, understanding of DFT implementation techniques, resolving signal and power integrity faults.
  • Ability to resolve a wide range of issues in creative ways on a regular basis
  • Excellent communication skills, verbal and written, and awareness of project management issues
  • Should be authorized to work in Canada
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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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Hiring Journey at Synopsys

Apply

When you apply to join us, your resume, skills, and experience are first reviewed for consideration.

Phone Screen

Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.

Interview

Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.

Offer

Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!

Onboarding

There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.

Welcome!

Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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