You Are:

A highly motivated, innovative, and independent ASIC/firmware digital verification engineer intern. You thrive in a collaborative environment, working as part of a highly experienced mixed-signal design team. You are passionate about technology and eager to contribute to the verification of current and next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products. You possess a solid understanding of digital circuit design and a basic understanding of C/C++ and RISC processors. You have hands-on experience in writing test cases in Verilog and SystemVerilog, and you are familiar with scripting languages like Python or Perl and working in a Linux environment. You have knowledge of high-speed digital and mixed-signal design, and you are familiar with industry digital verification methodologies such as VMM/UVM and version control systems like GIT/SVN/Perforce. Your organization and communication skills are exceptional, allowing you to interact effectively with teammates.

What You’ll Be Doing:

• Creating and updating test plans and test cases
• Writing modular constrained-random/coverage-driven Verilog, SystemVerilog, and UVM/VMM testbenches
• Writing SystemVerilog assertions
• Maintaining simulation regressions and debugging RTL and gate-level simulation failures
• Writing functional coverage and performing functional/code/assertion coverage analysis
• Tracking issues in Jira and documenting in Confluence

The Impact You Will Have:

• Enhancing the verification process for high-speed digital and mixed-signal designs
• Contributing to the successful development and delivery of high-end mixed-signal designs
• Ensuring the reliability and performance of current and next-generation products
• Improving the efficiency of the verification process through innovative test plans and methodologies
• Collaborating with an expert team to achieve project milestones and deliverables
• Supporting the continuous improvement of verification strategies and tools

What You’ll Need:

• Solid understanding of digital circuit design
• Basic understanding of C/C++ and RISC processors
• Hands-on experience in writing test cases in Verilog and SystemVerilog
• Familiarity with scripting languages (Python or Perl) and working in a Linux environment
• Knowledge of high-speed digital and mixed-signal design

Who You Are:

• Highly motivated and innovative
• Independent and proactive
• Excellent communicator with strong organizational skills
• Team player with a collaborative mindset
• Detail-oriented and able to manage multiple tasks

The Team You’ll Be A Part Of:

The Solutions Group at Synopsys provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. Our IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.