Analog Design, Principal Engineer

Job Responsibilities

• Review SerDes standards to develop novel transceiver architectures and sub-block specifications.
• Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets.
• Work across project and department teams to streamline design and verification strategies ensure overall design quality, efficiency and performance.
• Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
• Present & review simulation data from internal project teams.  Present results externally at industry panels or at customer reviews.
• Document design features and test plans.
• Consult on the overall electrical characterization of the SerDes IP product.  Analyze customer silicon data for design enhancements.  Propose solutions for post-silicon design updates.

Job Requirements

• PhD with 10+ years, or MSc with 12+ years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of study.
• Experience with FinFET technologies
• Extensive design experience with sub-circuits relevant to SerDes: 
  • Receive equalizers such as CTLE, DFE, FFE
  • DAC Based transmitters and ADC based receivers, DSP equalization
  • High speed clocking circuits such as PLL, VCO, DLL and phase interpolator
  • ADC and DAC
• In depth familiarity with transistor level circuit design - sound CMOS design fundamentals, experience with CMOS tape-outs
• Knowledge of SerDes, circuit and fabrication issues that directly impact customer use-cases.
• Aware of ESD issues (i.e. circuit techniques, layout).
• Familiarity with custom digital design (i.e. high-speed logic paths, Serializer, De-serializer).
• Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
• Knowledge of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.).
• Experience with tools for schematic entry, physical layout, and design verification.
• Knowledge of SPICE simulators and simulation methods.
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
• Excellent communication, presentation, and documentation skills

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.