We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are

You are a UCIe / Die-to-Die System Architecture Specialist who can work directly with customer architects to close real system-level chiplet and multi-die design decisions.

You are comfortable discussing UCIe subsystem architecture, die-to-die integration, IP configuration, protocol selection, packaging constraints, performance considerations, validation, interoperability, and deployment trade-offs.

This is a customer-facing presales technical role. You will help customers integrate die-to-die IPs into complex ASIC, SoC, and multi-die platforms, identify key requirements or gaps, and translate customer feedback into actionable input for Synopsys Product Management, R&D, and roadmap planning.

What You’ll Be Doing

• Own the technical architecture engagement for UCIe / die-to-die IP with strategic customers, from early chip let and multi-die platform requirements through architecture closure and initial deployment readiness.
• Work with customer architects and engineering teams to define suitable UCIe/ die-to-die sub system configurations for advanced ASIC, SoC, and multi-die platforms.
• Analyze system-level trade-offs related to protocol selection, bandwidth, latency, power, area, packaging considerations, validation, compliance, and interoperability.
• Translate customer platform requirements, integration constraints, and deployment feedback into clear input for Synopsys Product Management, R&D, and roadmap planning.
• Support technical closure of design wins by providing architecture guidance, configuration recommendations, risk assessment, and competitive positioning.
• Develop reusable technical material, application notes, and customer-facing guidance based on real engagement experience.
• Train FAEs and customer teams on UCIe architecture, die-to-die integration trade-offs, validation expectations, and deployment best practices.

The Impact You Will Have

• Improve the quality of UCIe / die-to-die design wins by ensuring customer chiplet and multi-die architectures are technically sound before commitment.
• Strengthen the Synopsys UCIe roadmap by feeding real customer system, packaging, protocol, and integration requirements into product planning and R&D execution.
• Reduce customer integration risk by identifying architecture, configuration, validation, interoperability, and implementation issues early.
• Help establish Synopsys as a trusted technical partner for next-generation AI, HPC, automotive, networking, and chip let-based platforms.
• Provide technical training to FAEs and key customers on UCIe architecture, die-to-die IP products,integration trade-offs, and deployment best practices.

What You’ll Need

• Bachelor’s and/or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or Computer Science.
• 5+ years of experience in semiconductor IP, SoC architecture, systems engineering, applications engineering, silicon validation, or customer-facing technical roles.
• Solid understanding of UCIe / die-to-die IP concepts and system integration considerations.
• Good system-level understanding of ASIC, SoC, and multi-die integration, with the ability to evaluate key performance and implementation trade-offs.
• Experience engaging directly with customer architects, design teams, validation teams, and technical decision-makers.
• Ability to translate ambiguous customer requirements into clear technical recommendations, product feedback, and closure plans.
• Strong technical communication skills, including clear written analysis, structured trade-off explanation, and ability to align customer, sales, product, and engineering teams.

Nice to Have

• Familiarity with one or more protocols commonly used in chip let and die-to-die systems, such as AXI, PCIe, CXL, CHI-C2C, CXS, or Streaming.
• Familiarity with multi-die architectures, advanced packaging technologies, and associated integration trade-offs.
• Prior experience selecting, using, designing, or supporting internal or external IP.
• Prior experience in application engineering or another direct customer-facing role.
• Familiarity with implementation or validation flows, including RTL design, verification, synthesis, static timing analysis, simulation, or silicon bring-up.

The Team You’ll be a Part Of

You will be part of our IP high-performance computing Solution Architecture team, a group of dedicated professionals who are passionate about technology and innovation. The team focuses on helping customers integrate more capabilities into SoCs faster, working collaboratively across geographic and organizational boundaries to drive revenue growth and accelerate business closure.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.