ASIC Digital Design, Manager

• Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solution
• Your passion and expertise will shape the next generation of product innovation, performance, and efficiency
• In this role, you will contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs
• You will manage a team of design engineers and work with Architect, Verification, Physical implementation, and Firmware teams
• You will lead the team to deliver the design and achieve the best timing, performance, and power goals

• BS/MS in Electrical Engineering with at least 6 years of experience in complex technical development

• 2 years of experience in people management, developing employees
• Experience with synthesizable Verilog and System Verilog design concepts and implementation
• Experience with front-end design flows including linting, synthesis, STA, cross-domain clocking, DFT, and power optimization techniques
• Exhibit excellent communication skills and be self-motivated
• Understanding of DDR memory and DDRPHY architecture is a plus

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.