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ASIC Digital Design, Manager

Nepean, Ontario, Canada
Engineering
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Overview

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.
DDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR PHY IP products.  All current and next-generation technologies are being developed by the DDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.
We are looking for ASIC Digital Design Manager to join Synopsys DDR PHY IP team to lead innovation and development of the world-class market-leading DesignWare DDR PHY IP solution.

Job Description
  • Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solution
  • Your passion and expertise will shape the next generation of product innovation, performance, and efficiency
  • In this role, you will contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs
  • You will manage a team of design engineers and work with Architect, Verification, Physical implementation, and Firmware teams
  • You will lead the team to deliver the design and achieve the best timing, performance, and power goals

Required Skills
  • BS/MS in Electrical Engineering with at least 6 years of experience in complex technical development
  • 2 years of experience in people management, developing employees
  • Experience with synthesizable Verilog and System Verilog design concepts and implementation
  • Experience with front-end design flows including linting, synthesis, STA, cross-domain clocking, DFT, and power optimization techniques
  • Exhibit excellent communication skills and be self-motivated
  • Understanding of DDR memory and DDRPHY architecture is a plus
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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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Hiring Journey at Synopsys

Apply

When you apply to join us, your resume, skills, and experience are first reviewed for consideration.

Phone Screen

Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.

Interview

Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.

Offer

Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!

Onboarding

There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.

Welcome!

Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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