ASIC Digital Design, Staff Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated and innovative digital design engineer with a deep understanding of ASIC development, modeling, and digital signal processing. You thrive in dynamic environments and excel at problem-solving. You possess a BSEE or MSEE and have accumulated over 5 years of experience in digital design or verification. Your expertise includes clock domain crossing techniques, synthesis, and static timing analysis (STA). You are also adept in low-power design techniques and have excellent organizational and communication skills to interact effectively with various design groups and customers. Additionally, experience with high-speed SerDes PHY components such as CDR, SAR ADC, and Fractional-N PLL, as well as knowledge in analog or mixed-signal design and digital signal processing, will be advantageous. You are eager to make a significant impact on industry-leading product architecture, quality, and customer engagement.

What You’ll Be Doing:

• Engaging in the design and verification of ASIC RTL at both chip and block levels.
• Collaborating with a mixed-signal design team to target the fastest PAM4 based SerDes PHY products.
• Applying clock domain crossing techniques in digital designs.
• Conducting synthesis and static timing analysis (STA) for high-performance digital designs.
• Implementing low-power design techniques to optimize performance and efficiency.
• Interfacing with different design groups and customers to ensure seamless project execution.

The Impact You Will Have:

• Contributing to the development of industry-leading mixed-signal products.
• Enhancing the performance and quality of high-speed SerDes PHY components.
• Driving innovation in digital and mixed-signal design methodologies.
• Influencing the architecture and implementation of flagship products.
• Improving customer satisfaction through high-quality design and verification.
• Mentoring and leading young talents across different domains, fostering a culture of continuous learning and growth.

What You’ll Need:

• BSEE or MSEE with 5+ years of digital design or verification experience.
• Strong understanding of clock domain crossing techniques.
• Proficiency in synthesis and static timing analysis (STA).
• Experience with low-power design techniques.
• Excellent organization and communication skills for effective interaction with design groups and customers.

Who You Are:

• A seasoned professional with a creative approach to problem-solving.
• A team player who thrives in collaborative environments.
• An effective communicator with strong interpersonal skills.
• Detail-oriented and committed to delivering high-quality work.
• A proactive learner who stays updated with the latest industry trends and technologies.

The Team You’ll Be a Part Of:

You will be part of a highly experienced mixed-signal design team dedicated to delivering high-end mixed-signal products. This team is focused on pushing the boundaries of technology and innovation, ensuring the highest standards of performance and quality in our products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.