ASIC Digital Design, Sr. Engineer

We are seeking a Digital Verification Engineer who will be involved for functional verification of High Speed interface IPs.  A dynamic personality with eager to learn, drive Pre-silicon verification activities, good knowledge of digital design & HDL implementation.

Job Description

• Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards
• IP/design blocks/Firmware Specification study and build/update verification plans as well as the test cases
• Build/update functional verification environments to execute the test plans
• Implement checkers, assertions, random test generators, high level transactional models and bus functional models (BFMs) as per the verification plan needs
• Performing simulation, random and direct stimulus development and coverage review
• Work closely with digital designers for debug and achieve the desired coverage

Requirements

• B.Tech/M.Tech with 2+ years of relevant experience
• Understanding of functional verification flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System Verilog
• Experience with System Verilog Assertions, code and functional coverage implementation and review
• Scripting and automation using TCL/PERL/Python
• Excellent debug and diagnostic skills

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.