We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities.
Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes.

The successful candidate:
- has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design.
- has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints
- has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. 
- Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements
- Independent, timely decision maker and able to cope with interrupts
- Knowledge of IP Subsystem implementation & FE flows are added advantages

5+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.