ASIC Physical Design, Staff Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Alternate Job Titles:
- ASIC Physical Design Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
Are you a highly motivated and experienced Physical Design Engineer with a passion for implementing and performing signoff verifications of digital blocks using the ASIC design flow (Gate2GDSII)? Do you thrive in dynamic environments and possess an in-depth understanding of the ASIC Physical design flow steps starting from Gate netlist? If so, you may be the ideal candidate for our team. We seek individuals who are detail-oriented, possess strong problem-solving skills, and have a collaborative mindset. A minimum of 5 years of relevant experience in the Physical design domain is essential, along with a B.E/B.Tech/M.Tech in ECE/EE. Exposure to Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV) and FinFET designs is highly desirable. Experience in working on IO integration with Wire-bond or Flip-chip design would be a significant advantage.
What You’ll Be Doing:
- Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows, including Design Initialization, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route, and chip finishing steps.
- Performing Physical Implementation of blocks starting from gate netlist till GDS out.
- Conducting signoff verifications, including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the implemented blocks.
- Writing MCMM and UPF for the block designs.
- Providing handoff data to other signoff closures like STA, Formality, Layout, and Reliability verification.
- Collaborating with cross-functional teams to ensure seamless project execution and delivery.
The Impact You Will Have:
- Ensuring the successful implementation and verification of digital blocks, contributing to the overall quality and performance of our ASIC designs.
- Enhancing the reliability and efficiency of our chip designs through meticulous verification processes.
- Driving innovation in chip design by implementing cutting-edge technologies and methodologies.
- Providing critical data and insights that support the successful signoff and integration of our chip designs.
- Contributing to the continuous improvement of our design flows and methodologies.
- Supporting the development of high-performance silicon chips that power a wide range of applications, from consumer electronics to advanced computing systems.
What You’ll Need:
- In-depth understanding of the ASIC Physical design flow steps starting from Gate netlist.
- Experience in Testchip implementation and testing exposure.
- Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV).
- Exposure to FinFET designs.
- Experience in working on IO integration with Wire-bond or Flip-chip design.
Who You Are:
- Detail-oriented and thorough in your approach to design and verification.
- Strong problem-solving skills and the ability to think critically.
- Excellent communication and collaboration skills, with the ability to work effectively in cross-functional teams.
- Adaptable and open to learning new technologies and methodologies.
- A proactive mindset with a passion for continuous improvement and innovation.
The Team You’ll Be A Part Of:
You will be joining a highly skilled and collaborative team focused on ASIC Physical Design. Our team is dedicated to pushing the boundaries of what's possible in chip design, leveraging the latest technologies and methodologies to deliver high-performance, reliable silicon solutions. Together, we work on complex design challenges and drive innovation in the semiconductor industry.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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