High-Speed SERDES Layout Specialist

Category Engineering Hire Type Employee Job ID 15023 Remote Eligible No Date Posted 02/01/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned professional in analog layout design, recognized for your expertise in high-speed custom layout and a deep understanding of SERDES (Serializer/Deserializer) architectures. With over 5 years of hands-on experience, you thrive in fast-paced, collaborative environments and are passionate about tackling complex challenges in advanced technology nodes. Your meticulous attention to detail and commitment to quality enable you to deliver robust, high-performance designs that meet stringent area, power, and yield targets. You possess a strong foundation in analog and mixed-signal layout, including experience with advanced floor planning, power grid optimization, and signal routing strategies. Your technical proficiency is matched by your effective communication skills, allowing you to work seamlessly with cross-functional teams across global locations. You take pride in mentoring junior engineers, sharing your knowledge, and contributing to a culture of continuous learning and innovation. Adaptable and proactive, you stay current with industry trends and are eager to drive layout methodology enhancements. If you are looking for an opportunity to make a significant impact in the semiconductor industry while working with cutting-edge technologies and a diverse team, Synopsys is the place for you.

What You’ll Be Doing:

• Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
• Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.
• Applying advanced analog layout techniques to meet stringent performance, area, and manufacturability requirements.
• Enhancing and automating layout flows to accelerate design cycles and improve overall design quality.
• Performing comprehensive layout verification, including DRC, LVS, ERC, ANT, ESD, DFM, and PERC checks to ensure all design and quality standards are met.
• Collaborating with Place and Route engineers to integrate analog layouts into complex top-level designs.
• Participating in design reviews with global teams to resolve issues and drive best practices.
• Contributing to package-level design activities, such as interposer and RDL (Redistribution Layer) layout.
• Mentoring and guiding junior engineers or interns, fostering technical growth and teamwork.

The Impact You Will Have:

• Delivering high-quality, high-performance analog IPs that are foundational to Synopsys’ leadership in chip design and integration.
• Driving innovation by optimizing layout methodologies for advanced technology nodes and high-speed interfaces.
• Contributing to the success of global customer projects through reliable, manufacturable, and scalable design solutions.
• Enhancing overall product quality and reliability through rigorous verification and design checks.
• Enabling faster time-to-market for Synopsys products by streamlining layout processes and reducing design iterations.
• Fostering a culture of knowledge sharing, mentorship, and continuous improvement within the team.

What You’ll Need:

• 5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.
• Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.
• Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).
• Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.
• Experience in package-level design, including interposer and RDL layout, is a plus.

Who You Are:

• An analytical thinker with a keen eye for detail and a passion for quality.
• Excellent communicator, able to work effectively with cross-functional, geographically dispersed teams.
• Proactive problem-solver who thrives in a dynamic and innovative environment.
• Collaborative team player who values diversity, inclusion, and continuous learning.
• Mentor and leader, enthusiastic about coaching and developing others.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in India, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.