SOC Engineering, Sr Staff Engineer

Alternate Job Titles:

• SOC Engineering Senior Staff Engineer
• Senior Staff Engineer, System-on-Chip
• Senior SOC Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned SOC Engineer with a proven track record in designing and implementing complex system-on-chip solutions. Your expertise spans across various facets of SOC architecture, including design, verification, and integration. You are passionate about pushing the boundaries of technology and thrive in a collaborative environment where you can share your knowledge and learn from others. Your problem-solving skills are exceptional, and you have a keen eye for detail, ensuring that every project you work on meets the highest standards of quality and performance. You are adaptable, able to navigate the dynamic landscape of technology, and are always eager to embrace new challenges and opportunities for growth.

What You’ll Be Doing:

• Designing and implementing advanced SOC architectures to meet specific project requirements.
• Collaborating with cross-functional teams to define and validate system specifications.
• Leading the verification process, ensuring that all SOC components function correctly and efficiently.
• Integrating various IP blocks and ensuring seamless communication between them.
• Conducting performance analysis and optimization to enhance SOC performance.
• Providing technical guidance and mentorship to junior engineers
  
• Job Description and Requirements

The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. 

As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors.

Responsibilities

• Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. 
• Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. 
• Lead team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems.
• Understand the design/architecture and lead the team to develop timing constraints for synthesis and timing.
• Work with peers to improve methodology and improve execution efficiency. 
• Ramp-up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers.
• Work with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.  
• Setup flows and methodologies to enable quick setup for RTL Quality checks, Synthesis and Formality. 
• Train the team in design concepts and root-cause analysis. 

Required

• B.E/B. Tech/M.E/M. Tech in electronics with 8+ years’ experience in RTL Design and Verification.
• Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. 
• Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. 
• Technical expertise in debugging and diagnosing violations and errors. 
• Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation.
• Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem. 
• Experience with planning and managing various activities related to RTL Signoff and Design. 
• Strong understanding of design concepts, ASIC flows and stakeholders.
• Good communication skills.
• Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on pushing the boundaries of SOC design and implementation. Our team is dedicated to developing high-performance, reliable SOC solutions that drive the next generation of technology. We value collaboration, continuous learning, and a commitment to excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.