Looking for highly motivated B. Tech. students with excellent academic records for  High Speed SERDES design and verification. As part of this team , you will be learning on digital design & verification of serial interface PHY IPs for serial standards like USB , PCIe, Ethernet with real time exposure to development on such products. You  will be learning protocols & specification as well as verification methodology for such systems. There’s going to be challenges to overcome with Out-of-box thinking, apply the ideas for design & verification of such products.

Requirements:

• Excellent digital design and implementation flow basics   
• RTL design & verification exposure with good skill of Verilog/System Verilog 
• Shell/Perl Scripting exposure
• A proactive team player with good written and verbal communication skills