Analog Design Engineer, Staff
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Analog Design Engineer, Staff
Job Responsibilities:
- Review most advanced SerDes standards and architecture documents to develop analog sub-block specifications.
- Identify and refine circuit implementations to achieve optimal power, area and performance targets.
- Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
- Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
- Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
- Present simulation data for peer and customer review.
- Mentor and Review the progress of junior engineers.
- Document design features and test plans.
- Consult on the electrical characterization of your circuit within the SerDes IP product.
Job Requirements:
- PhD with 3+ years, or MSc with 5+ years of SerDes/High-Speed analog design experience.
- In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
- Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
- Detailed design experience with several of the following SerDes sub-circuits:
receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC - Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
Should you require an accommodation, please contact hr-help-canada@synopsys.com.
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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