Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.

DDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR PHY IP products.  All current and next-generation technologies are being developed by the DDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power product.

We are looking for Senior ASIC Digital Design Engineer to join Synopsys DDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare DDR PHY IP solution.

Job Description

• Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solution
• Your passion and expertise will shape the next generation of product innovation, performance, and efficiency
• In this role, you will contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.

Required Skills

• BS/MS in Electrical Engineering with at least 2 years of experience in complex technical development 
• Experience with synthesizable Verilog and System Verilog design concepts and implementation
• Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
• Exhibit excellent communication skills and be self-motivated
• Understanding of DDR memory and DDRPHY architecture is a plus