Analog & Mixed Signal Layout Manager
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
This role will involve close interaction and collaborative teamwork with multiple functional groups (front end, analog, ASIC, CAD) and the product teams globally. The ideal candidate will be an excellent communicator and comfortable managing multiple tasks.
You will be part of an advanced physical design team developing full custom analog and ASIC layout of high-speed integrated circuits. As an Analog&Mixed-Signal Layout Manager you will be exposed to SerDes PHY design for PCIe, Ethernet and other protocols. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Ideal background would include hands-on analog layout or ASIC physical design experience with project management background and aptitude.
Main Responsibilities:
- Assures high quality of Analog & Mixed-Signal Layout implementations
- Owns cross team planning, collaboration, and coordination ensuring that geographically distributed teams are well-aligned
- Measure project and performance using appropriate systems, tools and techniques
- Establish and maintain relationships with cross-functional teams, internal and external customers
- Create and maintain comprehensive project documentation
- Deep understanding of physical design of analog and mixed signal CMOS circuits
- Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers
- Solid organizational skills including attention to detail and multi-tasking skills
- Autonomous, timely decision maker and able to cope with interrupts
- Experience with advanced FinFET nodes, TSMC 16 nanometer and below
- Experience with Design tool(s): Custom Compiler, Cadence Virtuoso or equivalent
- Verification tools: ICV, Calibre
- Strong working knowledge of MS Office Suite of applications
- MSEE or BSEE with a minimum of 8 years of related experience
- Exposure to SERDES design architectures, and layout
- Solid understanding of digital / mixed signal flows and SOC integration challenges
- Experience in working with Jira/Atlassian (or other such) tools
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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