ASIC Digital Design, Staff Engineer

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.  

Digital IP Verification Engineer 

We're looking for Digital IP Verification Engineer to join our Shanghai team. 
Does this sound like a good role for you? 

Responsibility: 

• Create UVM testbenches, tests, and constraints to ensure design correctness
• Design, develop, and maintain modular and reusable UVM testbenches for IP verification
• Define verification plan based on standard specifications
• Create randomized tests, adding constraints and directed tests to fully cover functionality
• Confirm test completeness through code and functional coverage
• Review testbenches, tests, and coverage with designers, architects
• Integrate tests and coverage within full environment

 Qualification: 

• Be familiar with SystemVerilog and UVM 

• Typically requires a minimum of 5 years of IP Verification experience 

• Understanding  in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plus 

• Be fluent in English, both speaking and writing 

• Has solid desire to learn and explore new technologies 

• Demonstrates good attitude in team work 
  
  Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.