ASIC Digital Design, Principal Engineer-13487

Category Engineering Hire Type Employee Job ID 13487 Base Salary Range $191000-$286000 Remote Eligible Yes Date Posted 03/12/2025

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a deep passion for digital design and innovation. With at least a decade of hands-on experience in high-performance ASIC development, you thrive in challenging environments that demand both technical mastery and strategic vision. You enjoy collaborating across multidisciplinary teams, leveraging your expertise in Verilog and SystemVerilog to architect and implement cutting-edge DDR PHY IP solutions. You are detail-oriented, analytical, and proactive in identifying design issues and driving them to resolution. Your communication skills enable you to clearly articulate complex technical concepts to both peers and customers, ensuring alignment and successful project outcomes. Self-motivated and adaptable, you embrace new technologies and methodologies, continuously seeking opportunities to improve design flows, processes, and product quality. Your commitment to excellence and innovation positions you as a trusted leader and mentor, eager to contribute to the ongoing success and advancement of Synopsys’ DDR PHY IP portfolio.

What You’ll Be Doing:

• Leading all phases of DDR PHY IP design, from initial specifications through to final productization and customer support.
• Architecting and implementing DDR PHY IP using synthesizable Verilog and SystemVerilog, ensuring robust, scalable, and efficient designs.
• Collaborating with Verification, Timing, DFT, and Power teams to conduct simulations, analyze results, and optimize design performance.
• Performing detailed analysis and resolution of Lint, CDC/RDC, DFT, timing, and power-related issues to ensure design integrity.
• Maintaining and enhancing design automation flows and processes to increase efficiency and reduce time-to-market.
• Providing expert-level customer support for integration of DDR PHY IP into their SoCs, troubleshooting and resolving technical challenges.

The Impact You Will Have:

• Drive innovation in DDR PHY IP technology, shaping next-generation memory solutions for global semiconductor leaders.
• Accelerate time-to-market for cutting-edge SoC designs by delivering robust, high-performance IP.
• Enhance product quality and reliability through rigorous verification and optimization practices.
• Empower customers with expert guidance and support, enabling successful integration and deployment of DDR PHY IP.
• Contribute to the evolution of design methodologies and automation, streamlining development workflows.
• Play a pivotal role in maintaining Synopsys’ leadership in the mixed-signal IP market, driving market share and customer satisfaction.

What You’ll Need:

• BS in Electrical Engineering (MS/PhD preferred) and 10-15+ years of experience in complex ASIC design and development.
• Expertise in synthesizable Verilog and SystemVerilog coding, architecture, and implementation.
• Proficiency with front-end design flows: linting, synthesis, timing analysis/closure, cross-domain clocking, DFT, and power optimization.
• In-depth understanding of DDR memory and DDR PHY architecture (preferred).
• Exceptional problem-solving skills and the ability to analyze and resolve technical issues in a fast-paced environment.

Who You Are:

• An effective communicator who can simplify complex concepts for diverse audiences.
• Self-motivated and proactive, with a strong sense of ownership and accountability.
• Collaborative team player who thrives in global, cross-functional environments.
• Detail-oriented, analytical, and organized in your approach to problem-solving.
• Adaptable and open to learning emerging technologies and methodologies.

The Team You’ll Be A Part Of:

Join a global, diverse, and highly skilled team at the forefront of DDR PHY IP development. The DDR PHY IP group at Synopsys is responsible for both digital and analog components, delivering high-performance, high-bandwidth, low-latency, and low-power solutions that define the industry standard. Collaborate with experts across design, verification, timing, DFT, and power optimization to create world-class IP that powers the most advanced SoCs in the market.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.