We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the test architecture of chips that actually ship, not just tape out, and you know that the difference between a clean production ramp and a yield nightmare often comes down to decisions made during DFT planning. You think in flows, not just features. When you see a large-scale SoC at an advanced node, you are already mapping out scan compression strategies, MBIST coverage, and where the timing bottlenecks will surface three months from now.

You are comfortable sitting with a customer's design team in Tokyo, walking through a failing ATPG run, isolating the root cause in a multi-block hierarchy, and proposing a fix that works within their schedule and their constraints. You do not need a perfect spec to get started. You ask the right questions, align with what the silicon actually needs, and build solutions that hold up under real manufacturing conditions.

Leading cross-functional work does not intimidate you. You have coordinated with vendors, debugged across time zones, and kept complex projects moving when the path forward was not obvious. At Synopsys, you will work on methodologies that shape how the industry tests chips at the edge of what is possible.

What You'll Be Doing

• Develop and refine DFT methodologies for large-scale SoC designs at advanced process nodes, including scan, MBIST, compression, and ATPG strategies using Synopsys TestMAX DFT and TestMAX SMS
• Execute top-level and block-level DFT implementation from specification through pattern delivery, covering MBIST insertion, scan compression, boundary scan, ATPG, and pattern simulation
• Debug DFT circuitry, verify interfaces across design blocks, and resolve simulation and timing issues that surface during integration and test validation
• Analyze complex technical challenges in real time and develop practical, deployable solutions that fit within customer schedules and design constraints
• Lead technical engagements with external vendors and collaborate across global engineering teams to drive methodology alignment and project success
• Script and automate DFT flows using Tcl and shell to improve efficiency, repeatability, and scalability across customer engagements
• Deliver technical guidance and methodology recommendations directly to customers, helping them navigate test challenges on cutting-edge designs

The Impact You Will Have

• Enable customers to achieve production-quality test coverage on chips that define next-generation AI, automotive, and high-performance computing applications
• Reduce time to market for complex SoCs by delivering proven DFT flows that work the first time and scale across multiple design blocks
• Shape how Synopsys DFT tools are applied in the field, feeding real-world insights back into product development and methodology evolution
• Build long-term technical relationships with leading semiconductor companies in Japan, becoming a trusted advisor on test strategy and implementation
• Drive adoption of advanced test techniques like scan compression and hierarchical ATPG that directly improve yield and reduce manufacturing cost
• Influence the success of customer tape-outs by catching and resolving test issues before they become silicon problems
• Contribute to the development of DFT best practices and reference flows that benefit Synopsys customers globally

What You'll Need

• Bachelor's degree or higher in Electrical Engineering, Computer Science, or a related technical field
• 3 to 15 years of hands-on experience in DFT and test flows using commercial EDA tools on large, complex SoC designs
• Deep knowledge of DFT methodologies including JTAG, ATPG, scan compression, and MBIST, with a strong understanding of how they interact in real designs
• Strong programming and automation skills in Tcl and shell scripting to build, customize, and optimize DFT flows
• Native-level Japanese and professional proficiency in English, with the ability to lead technical discussions and documentation in both languages
• Experience with Synopsys DFT tools such as TestMAX DFT and TestMAX SMS is a strong plus
• Demonstrated experience working with external partners, vendors, or global engineering teams on complex technical projects

Who You Are

• You can walk into a customer meeting, listen to a test coverage problem, and sketch out a solution approach on the whiteboard that the team actually believes will work
• You are the kind of engineer who does not just run ATPG, you understand why certain patterns fail, what that means for the design, and how to fix it without starting over
• When a project hits a timing closure issue that affects scan insertion, you do not wait for someone else to figure it out, you dig into the reports, talk to the right people, and find a path forward
• You are comfortable leading technical work across teams and geographies, keeping everyone aligned without needing to be the loudest voice in the room
• You know how to balance what is technically ideal with what is actually achievable given schedule, resources, and customer constraints
• You take ownership of the outcome, not just your piece of it, and you follow through until the patterns are delivered and the customer is confident in the result

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.