ASIC Digital Design, Staff Engineer

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, The cloud, 5G, The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world’s broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications and get differentiated products to market quickly with reduced risk.

Senior ASIC Digital Design Engineer

Synopsys is looking a creative, committed and talented engineer to fill a Senior R&D Engineer role in the RTL based IP Core design and verification. The candidate will be part of the Solutions Group at our Tokyo office, Japan and will be responsible for implementing and verifying RTL based IPs which are used in end-customer applications such as server farms, AI/ machine learning, automotive, etc. The candidate will work with our internationally based team of architects/ other design team/ other verification team members across multiple sites worldwide. The position offers learning and growth opportunities. This is a Senior Technical Individual Contributor role and offers challenges to work on technically challenging IP Cores. This work environment presents stimulating, challenging and rewarding work with exciting career development opportunities.

Job Responsibilities:

- Design Engineer

- Understand standard specifications

- Understand product functional specification and architecture

- Make architecture judgments on the RTL design

- Implement RTL based IP Core

- Verification Engineer

- Make verification strategy and plan

- Make methodology and architecture judgments on the testbench

- Implement testbench infrastructure and verification components

- Make verification item list and coverage/ checker definition

- Create reports that have "visible" metric of verification progress

- Common

- Breakdown own tasks and make plan and schedule

- Coordinate and drive the design review meeting

- Perform technical top person role

Key Qualifications:
- Design Engineer

- Hands on experience with creating micro-architecture/ detailed design from Functional Specifications

- Verification Engineer

- Hands on experience in creating Test Environment from Functional Specifications using UVM/VMM/OVM

- Hands on experience in creating Test Planning of constraint random verification and Coverage closure and Failure analysis

- Proficient in System Verilog and UVM, Object oriented coding and verification

- Common

- Hands on experience with Verilog/ System Verilog coding and Simulation tools

- Understanding of SoC/ASIC design flows, Backend processes and procedures

- Understanding of one or more of protocols: DDR/PCIE/AMBA (AMBA2, AXI, CHI)/ SD/ eMMC/ Ethernet/ USB/ MIPI

- Hands on experience with Unix operation

- English communication skills

- Ability to work autonomously, precisely and to drive innovation

- In addition, the candidate should have good communication skills, will be a team player and will have good problem-solving skills

- Advantage

- Have BSEE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience

- Hands on experience in Formal verification is an added advantage

- Understanding of C/C++ language, Perl, Python and TCL scripting is an added advantage

- Understanding of firmware/embedded software development is an added advantage

- Experience of working with Functional safety, ISO26262, FMEDA is an added advantage