ASIC Digital Design Engr, II

• MSEE graduate or BSEE plus minimum 3 years of digital design and verification experience in the industry
• Good experience in writing block-level test-cases including constrained directed random tests
• Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required
• Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
• Scripting experience in Shell, Perl, Python and TCL is a plus
• Good theoretical and practical understanding of digital signal processing and data recovery circuits is required
• Good communication skills for interacting between different design groups and customer support teams are required
• Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines
• Resolves issues in creative ways and exercises self-directed judgment in selecting methods and techniques to obtain solutions
• May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise
• Must exhibit ability to produce good results as autonomously and as a team contributor

• RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog
• Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
• Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
• Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols
• Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.