ASIC Digital Design, Staff Engineer

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. 

Digital IP DDR Controller Team is seeking for a highly motivated and innovative digital design verification engineer with knowledge of ASIC development flow. The candidate would be working as part of a particularly experienced digital IP design and verification team, targeting the current and next generation DDR memory controller. Theoretical and practical background in DDR memory is a solid plus. The position offers an excellent opportunity to work with a team of professional engineers who are responsible for delivering enhanced universal DDR memory controller from defining specification to performing functional and performance tests. 

Key Qualifications

BSEE with 8+ years or MSEE with 5+ years of relevant experience in the industry 

Good experience in preparing verification strategy and writing block-level test-cases including constrained directed random tests 

Must have good knowledge of scripting in Shell, Perl, Python and TCL is a plus 

Should have good understanding on ASIC design (connecting modules, simple coding style, etc.)

Theoretical and practical background in LPDDR/DDR memory is a solid plus 

Knowledge of high-speed interface protocols, such as CHI, AXI, AHB, DFI, is a solid plus 

Resolves issues in clever ways and exercises impartial judgment in selecting methods and techniques to obtain solutions

Must be self-motivated, proactive, and able to guarantee good design quality while meeting tight deadlines

May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise

Good communication skills for interacting between different groups 

Preferred Experience

Defining verification strategy and writing test plan with high quality 

Building complex testbench and writing test-cases in System Verilog 

Debugging failure and collecting coverage to fulfill feature verification requirement 

Interacting with Application Engineers for customer support