Layout Design Engineer

You will be part of an R&D team developing high speed analog and mixed-signal layout for SerDes IP. You’d leverage your strong understanding of EDA tools, advanced nodes and layout as well as knowledge of ESD and Latch-up. You will work with a cross functional layout team of analog and digital layout designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.

Responsibilities:
Design top level layout with advanced process nodes.
Provide solution for difficult ESD/Latch-up/ANT issues in layout
Stick to workflow and deliver database with high quality
Take part in analog layout and design communication, detecting problems
Discuss and exchange skill sets with global designers
Requirements:
Bachelor’s degree or above
Major in Microelectronics, Electronic Engineering or Electronic related fields
Mastering in using EDA tool for layout drawing
Proficient in top-level floorplan and connection
Adept at ESD/Latch-up and solve related problems
Use English to communicate with layout designer from global sites
Preferred experience:
3+ years of experience in layout design;
Knowledge of advanced nodes;
SoC level experience is prior;

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.