ASIC Digital Design, Sr Engineer

Category Engineering Hire Type Employee Job ID 16074 Remote Eligible No Date Posted 03/16/2026

Alternate Job Titles:

• Senior ASIC Engineer
• Senior Digital Design Engineer
• RTL Design Engineer
• SoC Design Specialist
• Senior IP Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a deep passion for digital design, architecture, and execution excellence. You have demonstrated ownership over complex IP/block-level design projects, consistently delivering high-quality, synthesis/timing-clean RTL from specification to tape-out. Your expertise spans RTL coding in Verilog/SystemVerilog, power-aware design, clock domain crossings, and reset strategies. You thrive in collaborative environments, working seamlessly with cross-functional teams including verification, architecture, and physical design. As a senior member, you are adept at mentoring junior engineers, reviewing code, and promoting best practices within your team. You possess a strong schedule discipline and risk management capability, ensuring timely delivery and smooth integration of your design blocks. Your proficiency in scripting and automation enables you to innovate design methodologies and streamline workflows. You are comfortable navigating ambiguity and driving technical discussions, planning, and reviews to achieve project milestones. With a keen eye for detail, you emphasize documentation and communication, contributing to a culture of continuous improvement. If you are motivated by challenges, eager to make a tangible impact, and ready to lead by example, Synopsys offers you the platform to shape the future of technology.

What You’ll Be Doing:

• Driving IP/block-level digital design from specification through micro-architecture, RTL coding, and quality checks to tape-out.
• Delivering high-quality, fully verified, synthesis and timing-clean RTL for complex IP blocks.
• Collaborating closely with verification, physical design, and DFT teams to ensure seamless integration and customer delivery.
• Executing project roadmaps, quality goals, and release milestones with strong schedule discipline and risk management.
• Innovating design methodologies, automation flows, and best practices for continuous improvement.
• Mentoring junior engineers, reviewing code, and enhancing design guidelines and documentation.
• Efficiently debugging complex issues across design, synthesis, simulation, CDC, and firmware.

The Impact You Will Have:

• Enable delivery of world-class silicon IP and SoC solutions, powering next-generation products in AI, automotive, and consumer electronics.
• Drive technical excellence and innovation within Synopsys, raising the bar for digital design quality and reliability.
• Strengthen team collaboration and knowledge sharing, fostering a culture of mentorship and continuous improvement.
• Accelerate project timelines and ensure on-time, high-quality releases to customers and partners.
• Contribute to the development of advanced methodologies and automation, enhancing efficiency across the organization.
• Support the integration of industry-leading protocols and interfaces, expanding Synopsys’ technology portfolio.

What You’ll Need:

• Expert-level proficiency in RTL coding using Verilog/SystemVerilog.
• Strong understanding of synchronous design, power-aware design, clock domain crossings, and reset strategies.
• Experience translating architectural specifications into optimized RTL implementations.
• Expertise with synthesis, constraints, and timing closure (STA fundamentals).
• Hands-on experience with lint/CDC tools, UPF/low-power flows, pipeline design, multicycle, and false-path handling.
• Good understanding of DFT concepts and SoC-level integration flows.
• Experience with ARM/AMBA (AXI/AHB/APB) protocols or PCIe/USB/DDR interface IPs.
• Proficiency in scripting and automation using Python, Perl, or TCL.
• Ability to write basic SystemVerilog testbenches, assertions, or review coverage.

Who You Are:

• Strong ownership mindset and execution maturity.
• Excellent debugging, problem-solving, and analytical skills.
• Effective communicator with robust documentation skills.
• Collaborative and supportive team player.
• Open to mentoring and guiding junior engineers.
• Adaptable, able to manage ambiguity and shifting priorities.
• Disciplined in managing schedules, risk, and quality.

The Team You’ll Be A Part Of:

You will join a highly skilled and diverse engineering team focused on delivering cutting-edge digital IP and SoC solutions. The team fosters innovation, collaboration, and continuous learning, working on industry-leading projects that advance the state-of-the-art in chip design. You will have the opportunity to partner with experts in verification, architecture, physical design, and DFT, contributing to a vibrant and supportive environment where your growth and impact are valued.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.