ASIC Digital Design, Sr Staff Engineer

Category Engineering Hire Type Employee Job ID 13682 Remote Eligible No Date Posted 18/12/2025

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced ASIC verification professional with a passion for leading technical teams and driving excellence in digital design. You possess a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development. Your expertise is matched by your ability to collaborate effectively with cross-functional teams, including architects, RTL designers, and program managers, ensuring that every project you lead meets the highest standards of quality and innovation.

You thrive in dynamic environments, balancing technical leadership with hands-on verification work. Your curiosity drives you to stay ahead of emerging technologies and industry trends, while your mentorship empowers others to grow their skills. You are comfortable taking ownership of complex verification deliverables, making data-driven decisions, and advocating for best practices in every stage of the design and verification flow. Your communication skills enable you to articulate technical concepts to diverse audiences, fostering a culture of transparency and continuous improvement.

With your background in Electrical or Electronics and Communication Engineering and extensive experience in ASIC verification—especially in DDR IP projects—you are ready to make a significant impact at Synopsys. You are committed to delivering robust, high-performance solutions that will shape the next generation of intelligent systems.

What You’ll Be Doing:

• Technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.
• Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.
• Performing verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.
• Developing and implementing advanced test plans and test environments at both unit and system levels.
• Coding and debugging test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
• Extracting and reviewing functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.
• Managing regressions and contributing to the continuous improvement of verification strategies and test environments.

The Impact You Will Have:

• Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores for our customers.
• Drive the development of cutting-edge technologies that enable the Era of Smart Everything, from AI to automotive applications.
• Empower the creation of high-performance silicon chips and software content, fueling innovation across multiple industries.
• Collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.
• Bolster Synopsys' leadership in chip design and software security by ensuring our IP verification methodologies set industry standards.
• Directly influence the success and reputation of the DesignWare IP Verification R&D team through technical excellence and innovation.

What You’ll Need:

• BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience.
• Demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.
• Proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.
• Advanced skills in developing and implementing rigorous test plans, checkers, and assertions.
• Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.
• Experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.
• Hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.

Who You Are:

• Collaborative leader who inspires and mentors team members to achieve their best.
• Analytical thinker with strong problem-solving skills and a commitment to quality.
• Exceptional communicator, able to bridge technical and non-technical stakeholders.
• Self-motivated and proactive, with a passion for continuous learning and professional development.
• Adaptable and resilient in the face of complex challenges and changing priorities.

The Team You’ll Be A Part Of:

You will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys’ leadership in semiconductor IP. The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards. Collaboration, innovation, and a drive for excellence define our culture.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.