IP Design Technical Lead/ Staff ASIC RTL Design Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Category Engineering Hire Type Employee Job ID 16586 Remote Eligible No Date Posted 04/08/2026
Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.
LPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products. All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.
We are looking for Staff ASIC Digital Verification Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.
Job Description
•Defining and tracking Verification test plans
•Designing and writing constrained-random SystemVerilog testbenches using UVM
•Writing SystemVerilog assertions
•Writing functional coverage
•Debugging RTL and GLS failures
•Code coverage Analysis
•Providing mentoring and guidance to less experienced team members
Required Skills
•BSEE in EE with 5+ years of industry experience
•Digital verification in UVM environment Formal Verification is a plus
•Understanding of memory and memory PHY architecture
•Knowledge of DFI, Memory Controller or Memory Subsystem
•Verilog, System Verilog and Perl/Python scripting skills
•Debugging skills
•Demonstrates good communication and problem-solving skills
•Understanding of high-speed interface protocols is a plus
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
Hiring Journey at Synopsys
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View all job opportunities here
View all job opportunities here