We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a dynamic leader with a passion for technology and a proven track record in formal verification. You thrive in collaborative environments, bringing together diverse talents and perspectives to solve complex challenges. Your expertise spans RTL design and verification methodologies, and you have a deep understanding of assertion-based verification. You are adept at managing and mentoring medium to large teams, fostering a culture of innovation, inclusion, and continuous learning. With a strategic mindset, you excel at building partnerships with customers, driving technical reviews, and identifying opportunities for differentiation. Your communication skills enable you to articulate complex technical concepts clearly to both internal and external stakeholders. You are committed to delivering high-quality solutions that advance customer productivity and satisfaction. As an advocate for diversity, you ensure that every team member feels valued and empowered. Your leadership inspires others to pursue excellence, adapt to evolving industry requirements, and embrace new technologies. You are resilient, adaptable, and eager to take on new challenges in a fast-paced, impact-driven environment. Your vision aligns with Synopsys’ mission to transform the future through technological innovation, and you are ready to make your mark as a Senior Manager in Formal Verification Applications Engineering.

What You’ll Be Doing:

• Managing a team of product application engineers to champion the adoption of Synopsys Formal Verification Applications across strategic customer accounts.
• Developing and nurturing strategic partnerships with top-tier customers to understand and address their evolving verification needs.
• Driving and facilitating management and technical review meetings with customers, ensuring alignment and value delivery.
• Performing competitive analysis to inform the development of innovative formal verification technologies and methodologies.
• Collaborating closely with R&D and Product Management teams to define and implement new verification flows and functionalities.
• Scoping and executing formal consulting services, ensuring successful delivery and customer satisfaction.
• Defining formal verification methodologies to enhance customer productivity and streamline verification processes.
• Leading the development of assertion IPs tailored to meet specific customer requirements.

The Impact You Will Have:

• Accelerate the adoption of industry-leading formal verification solutions, enabling customers to achieve robust, high-quality silicon designs.
• Strengthen Synopsys’ reputation as a trusted partner for verification innovation and excellence.
• Drive customer success by delivering tailored consulting services and assertion IPs that address complex verification challenges.
• Enhance productivity and efficiency for customers through advanced formal methodologies and flows.
• Influence the direction of formal verification technology by collaborating with R&D and Product Management teams.
• Foster a culture of technical excellence and inclusion within your team, empowering members to grow and contribute meaningfully.
• Enable strategic customers to meet critical industry requirements such as design security, automotive safety, and verification signoff.

What You’ll Need:

• Bachelor’s degree in Electrical Engineering from a reputed institution; postgraduate degree preferred.
• 15+ years of industry experience in RTL design or verification, particularly using simulation-based methodologies.
• At least 5 years of experience managing medium to large engineering teams.
• In-depth knowledge of assertion-based verification using both formal and simulation methods.
• Strong understanding of hardware design languages (Verilog/VHDL) and micro-architecture.
• Expertise in Unix/Linux automation shell scripting (bash, csh) and programming languages such as Tcl, Perl, and Python.
• Experience in formal property verification testbench development, floating point arithmetic operations, C/C++, IEEE math libraries, security architecture, automotive safety (FuSa), and verification signoff with formal.
• Exceptional oral and written communication skills to engage effectively with customers and internal teams.

Who You Are:

• Inclusive and empathetic leader who champions diversity and fosters a supportive team environment.
• Strategic thinker with strong problem-solving abilities and a proactive approach to challenges.
• Collaborative and adaptable, able to partner across functions and with global customers.
• Highly organized, detail-oriented, and able to manage multiple priorities efficiently.
• Motivator who inspires team members to pursue continuous learning and professional growth.

The Team You’ll Be A Part Of:

The Formal Verification Team is a core part of Synopsys’ EDA Group, dedicated to deploying high-quality verification solutions for industry-leading customers. The team tackles diverse verification challenges, including property verification, data path verification, clock-gating checks, design security, and automotive safety. We foster a collaborative environment where every member can explore different aspects of design verification and contribute to innovative solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.