Sr Engineer - Standard Cell & Characterization

Category Engineering Hire Type Employee Job ID 17255 Remote Eligible No Date Posted 05/06/2026

Standard Cell & Characterization, Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the characterization world, and you know that a standard cell library is not just a collection of files. It is the foundation every SoC team builds on, and when your Liberty models are wrong or your correlation is off, someone downstream pays for it in silicon respins or missed timing closure. You have debugged enough NLDM versus CCS mismatches to know where the bodies are buried, and you can spot a bad AOCV model from the regression results alone.

You do not just run characterization flows. You understand what the numbers mean, why a sequential cell behaves differently under aging, why a level shifter needs special handling, and how to explain a correlation gap to a design team that is already behind schedule. You have worked across multiple nodes, you have seen methodologies evolve, and you know when to follow the recipe and when to rewrite it because the recipe is the problem.

Mentoring does not feel like extra work to you. When a junior engineer hits a wall on ECSM modeling or does not understand why their spice correlation is drifting, you can guide them through it without taking over. At Synopsys, you will work on libraries that ship to customers building the most advanced chips in the world, and the quality bar is exactly where you want it to be.

What You'll Be Doing

• Characterize and model standard cell libraries for advanced technology nodes, generating Liberty models across NLDM, NLPM, CCS timing, CCS noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and electromigration
• Handle characterization for combinational cells, sequential cells, clock gating cells, synchronizers, retention cells, level shifters, power gating cells, always-on cells, fillers, and decap cells
• Diagnose and resolve correlation issues across characterization, static timing analysis (STA), and spice simulation, working with design teams to close gaps
• Execute QA checks, regression analysis, and release validation to ensure library deliverables meet quality and accuracy standards before customer delivery
• Coordinate project execution within the Library Characterization team, including task assignments, milestone tracking, and release scheduling
• Drive methodology improvements and automation initiatives to enhance characterization flow efficiency, accuracy, and turnaround time
• Mentor junior engineers on characterization techniques, Liberty modeling best practices, and troubleshooting correlation and quality issues

The Impact You Will Have

• Enable accurate timing closure and power analysis for SoC designs across leading-edge technology nodes by delivering high-quality Liberty models
• Reduce design iteration cycles for customers by ensuring tight correlation between characterized models and silicon behavior
• Accelerate library delivery timelines through methodology enhancements and automation that eliminate manual bottlenecks
• Improve library quality and consistency across multiple nodes by establishing robust QA and regression frameworks
• Build team capability and reduce ramp time for new engineers through structured mentorship and knowledge transfer
• Support successful customer tapeouts by resolving critical characterization and correlation issues that impact timing and power signoff
• Shape the future of Synopsys library characterization methodology by identifying and implementing flow improvements based on real project learnings

What You'll Need

• Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related field
• 5+ years of hands-on experience in standard cell library characterization and Liberty modeling
• Deep understanding of Liberty model formats including NLDM, NLPM, CCS, ECSM, and advanced variation models like AOCV, POCV, and spatial OCV
• Proven ability to debug and resolve correlation issues across characterization, STA tools, and spice simulation
• Experience characterizing a range of cell types including sequential cells, level shifters, retention cells, power gating cells, and clock gating cells
• Solid grasp of QA processes, regression testing, and release management for library deliverables
• Experience with aging models, electromigration modeling, or advanced node challenges (3nm, 5nm, 7nm) is a plus

Who You Are

• You can look at a Liberty file and immediately spot whether the delay arcs make sense for the cell type, and you know which corners to check first when correlation breaks
• When a design team reports a timing mismatch, you do not wait for a formal ticket. You pull the models, check the characterization setup, and start narrowing down the root cause
• You are organized enough to manage multiple library releases across different nodes without losing track of what is in QA, what is waiting on spice data, and what is ready to ship
• Explaining a complex characterization issue to a junior engineer or a customer FAE does not frustrate you. You can break it down, show the data, and make sure they understand the why, not just the what
• You push back when a characterization request does not make technical sense or when a release timeline does not leave room for proper validation, and you do it with clarity and data
• You see automation as part of the job, not a side project. If you are running the same manual check five times a week, you are already thinking about how to script it

The Team You'll Be Part Of

You will join the Library Characterization team in Bangalore, a group responsible for characterization, validation, QA, and release management of advanced standard cell libraries across multiple technology nodes. The team works closely with foundry partners, internal IP teams, and customer-facing application engineers to deliver libraries that meet the accuracy and quality standards required for leading-edge SoC design. Your recruiter will share more about the team structure and current project portfolio during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.