We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. You have a proven track record of working on advanced nodes under 5nm and are proficient in low-power, high-performance design. Your familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. You are adept at scripting languages such as TCL, Perl, and Python, and hold a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience. You thrive in a dynamic environment, constantly seeking to push the boundaries of technology and improve quality of results. Your ability to work both independently and collaboratively makes you an invaluable asset to any team.

What You’ll Be Doing:

• Developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs.
• Utilizing advanced technologies and tool features to enhance quality of results and streamline the implementation process.
• Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs.
• Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler to solve critical design challenges.
• Collaborating with a global team to stay ahead of technological advancements and design complexities.
• Driving continuous improvement in PPA and turnaround time (TAT) metrics.

The Impact You Will Have:

• Advancing the state-of-the-art in high-performance core and IP implementation.
• Enhancing the performance and efficiency of Synopsys' design methodologies and tools.
• Enabling the development of cutting-edge semiconductor technologies at advanced nodes.
• Contributing to the successful delivery of high-quality, high-performance IPs to the market.
• Driving innovation and pushing the boundaries of what is possible in chip design.
• Supporting Synopsys' mission to lead in chip design, verification, and IP integration.

What You’ll Need:

• Deep knowledge of synthesis, timing closure, power optimization, and constraints management.
• Experience with low-power, high-performance design at advanced nodes under 5nm.
• Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX.
• Familiarity with scripting languages such as TCL, Perl, and Python.
• BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience.

Who You Are:

You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. You possess excellent problem-solving skills and have a keen eye for optimizing design processes. Your ability to collaborate effectively with a global team and communicate complex technical concepts clearly sets you apart. You are driven by a desire to continuously improve and make a significant impact in the field of semiconductor design.

The Team You’ll Be A Part Of:

You will join a growing global team at Synopsys focused on advancing the state-of-the-art in high-performance core and IP implementation. This team is dedicated to developing innovative methodologies to implement CPUs, GPUs, and interface IPs that deliver higher performance with lower power consumption. The team leverages advanced technologies and tool features to improve quality of results and simplify the implementation process. You will work alongside experts responsible for developing PPA methodologies for complex IPs, tackling dynamic challenges, and staying ahead of technological advancements.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.