Staff ASIC Digital Design Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Staff ASIC Digital Design Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a highly motivated and experienced ASIC Digital Design Engineer with a passion for innovation and technology. With at least 6 years of experience in digital design, you have a solid engineering foundation and a deep understanding of the full design cycle from RTL to GDSII. You are proficient in Verilog RTL coding and have experience with Lint/CDC/RDC. You possess strong knowledge of high-speed SERDES protocols, high-performance digital design, low-power design, and high-speed clock design and distribution. Your software and scripting skills in Perl, Tcl, Python, etc., are commendable, and you are adept at CAD automation methods. You excel at interfacing with larger product teams and customers, contributing to project tape-outs, and driving improvements and fixes back to product lines. Your expertise in the Synopsys tools, flows, and methodologies required to execute design projects makes you a valuable asset to our team.
What You’ll Be Doing:
- Thoroughly understanding the Subsystem configuration chosen by the customer and identifying the optimal Functional and Scan/DFT clock architecture.
- Generating Subsystem Functional and Scan signoff quality constraints and validating constraints to ensure quality and completeness.
- Developing DFT architecture for internal subsystems.
- Performing Synthesis & Post placement timing closure feasibility to identify and address bottlenecks.
- Driving improvements and fixes back to the product lines.
- Providing post-sales and presales expert consulting.
- Contributing to Serdes subsystem hardening services projects.
The Impact You Will Have:
- Enhancing the quality and efficiency of our digital design processes.
- Ensuring high-quality and complete validation of constraints for our projects.
- Improving the performance and reliability of our Serdes subsystem solutions.
- Contributing to successful project tape-outs and customer satisfaction.
- Driving continuous improvements in our product lines and methodologies.
- Providing expert consulting to support our sales and customer success teams.
What You’ll Need:
- Solid engineering understanding of the underlying concepts of IC design.
- Strong knowledge of the full design cycle from RTL to GDSII, including development of timing constraints.
- Good understanding of the implementation flows and methodologies for deep sub-micron designs.
- Expertise in Verilog RTL coding, as well as Lint/CDC/RDC.
- Exposure and a good understanding of High Speed SERDES protocols.
- Experience in high-performance digital design and CAD, high-speed design, low-power design, high-speed clock design and distribution.
- Proven experience contributing to project tape-outs.
- Good software and scripting skills (Perl, Tcl, Python, etc.); knowledge of CAD automation methods.
Who You Are:
You are a seasoned professional with a comprehensive understanding of ASIC digital design and implementation. You work with minimal supervision, take initiative, and have a track record of delivering high-quality results. You are a strong communicator, capable of working with diverse teams and customers. Your analytical skills and problem-solving abilities are top-notch, allowing you to navigate complex design challenges effectively.
The Team You’ll Be A Part Of:
You will be part of the Synopsys Serdes Subsystem Digital Implementation Team, a group of highly skilled engineers focused on delivering cutting-edge digital design solutions. Our team is dedicated to innovation, quality, and customer success, working collaboratively to achieve our goals and drive technological advancements.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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