Staff R&D Engineer - High Performance Core & IPs

Category Engineering Hire Type Employee Job ID 13361 Remote Eligible No Date Posted 10/11/2025

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate engineering professional with a deep drive to push the boundaries of semiconductor technology. With a background in physical design and a strong grasp of advanced methodologies, you thrive in dynamic environments where innovation is key. You have extensive experience implementing high-performance interface IPs and are eager to contribute to the development of CPUs, GPUs, and other complex systems at cutting-edge technology nodes. You excel at collaborating with global expert teams and enjoy tackling both flow development and hands-on implementation challenges. Your curiosity and desire to learn new technologies empower you to adapt quickly to the ever-evolving semiconductor landscape. You have demonstrated success in managing synthesis, timing closure, and power optimization, and possess a solid understanding of constraints management and state-of-the-art tool flows. Your scripting prowess enables you to automate and streamline design processes, while your problem-solving acumen allows you to overcome technical hurdles efficiently. You communicate clearly and confidently in English, making you a valued contributor in cross-functional settings. Your motivation, enthusiasm, and results-oriented mindset propel you to deliver best-in-class PPA and TAT metrics, and you take pride in contributing to the next generation of high-performance IPs. With a BS or MS in Electrical Engineering or a related field and at least 9 years of relevant experience, you are ready to make a significant impact at Synopsys.

What You’ll Be Doing:

• Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.  
• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.  
• Drive flow development and optimization to improve design quality and predictability.  
• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).  
• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.  
• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.  
• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.  
• Participate in technical reviews and provide guidance on best practices for low-power, high-performance design.

The Impact You Will Have:

• Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.  
• Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.  
• Enhance the predictability and simplicity of implementation processes for complex interface IPs.  
• Accelerate the adoption of next-generation design technologies and tools across the industry.  
• Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.  
• Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.  
• Mentor and collaborate with peers, contributing to a culture of knowledge sharing and technical excellence.

What You’ll Need:

• Minimum 5 years of experience in physical design, with a focus on high-performance and low-power methodologies.  
• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.  
• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.  
• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.  
• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.  
• Bachelor’s or Master’s degree in Electrical Engineering or related field.

Who You Are:

• Self-motivated and enthusiastic about continuous learning and growth.  
• Excellent communicator, able to articulate complex technical concepts in English.  
• Collaborative team player who thrives in diverse, global environments.  
• Results-oriented, with a strong drive to achieve and exceed targets.  
• Analytical thinker and creative problem solver.  
• Adaptable to change and comfortable with fast-paced, dynamic challenges.

The Team You’ll Be A Part Of:

You will join a dynamic, global team of experts dedicated to advancing the state-of-the-art in high-performance cores and IP implementation. The team is at the forefront of developing innovative methodologies and leveraging Synopsys’ industry-leading tools to solve the most critical design challenges in semiconductor technology. Together, you’ll collaborate on flow development, process optimization, and the implementation of advanced interface IPs, all while working on the latest technology nodes and driving best-in-class results for Synopsys and its customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.