Standard Cell Layout Engineer, Staff Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Alternate Job Titles:
- Standard Cells Layout Engineer
- Digital Layout Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced and highly motivated professional with a strong technical background in standard cells layout design. You thrive in collaborative environments, working closely with cross-functional teams to deliver high-quality layout designs. Your expertise in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler, allows you to create and optimize complex layouts efficiently. You are well-versed in physical verification processes and design rule checks, ensuring the integrity and manufacturability of your designs. Your problem-solving skills and systematic approach enable you to tackle challenges effectively. You are a lifelong learner, staying updated with the latest industry trends and advancements in standard cells layout design. Your excellent communication and interpersonal skills make you a valuable team player, contributing to the success of your projects and the organization as a whole.
What You’ll Be Doing:
- Collaborate with cross-functional teams to develop and implement layout designs for digital circuits.
- Create and optimize layout designs using industry-standard EDA tools.
- Perform physical verification and design rule checks to ensure design integrity and manufacturability.
- Participate in design reviews and provide feedback to improve design quality.
- Work closely with circuit designers to understand design specifications and constraints.
- Contribute to the development and enhancement of layout design methodologies and best practices.
- Stay updated with the latest industry trends and advancements in standard cells layout design.
The Impact You Will Have:
- Ensure the delivery of high-quality layout designs for Logic Libraries IP development, integral to SOC subsystems.
- Enhance the manufacturability and reliability of our silicon lifecycle monitoring solutions.
- Drive innovation in layout design methodologies and best practices.
- Collaborate effectively with circuit designers to meet design specifications and constraints.
- Contribute to the overall success of the Logic Libraries IP group.
What You’ll Need:
- Bachelor’s or master’s degree in electronics engineering or a related field.
- 6+ years of experience in standard cells layout design for digital circuits.
- Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler.
- Exceptional knowledge of layout design methods, techniques, and methodologies.
- Experience with physical verification tools, such as ICC2.
- Understanding of semiconductor process technologies and their impact on layout design.
- Excellent problem-solving and systematic skills.
- Ability to work effectively in a team-oriented environment.
- Good communication and interpersonal skills.
Who You Are:
You are a detail-oriented and innovative thinker with a passion for excellence in layout design. Your collaborative spirit and ability to communicate effectively make you a key asset to any team. You are adept at balancing technical expertise with creativity, driving continuous improvement and innovation in your work. Your proactive approach and dedication to staying current with industry advancements ensure that you are always at the forefront of technology.
The Team You’ll Be A Part Of:
You will be part of the Logic Libraries IP group, a dynamic team focused on developing high-quality layout designs that are integral to SOC subsystems. Our team thrives on collaboration, innovation, and a commitment to excellence. We work closely with circuit designers and other cross-functional teams to ensure our designs meet the highest standards of quality and manufacturability.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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