ASIC Digital Design, Sr Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Alternate Job Titles:
- ASIC Design Engineer
- Digital Design Engineer
- Senior ASIC Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature, and other monitoring IPs within SOC subsystem. Synopsys is a market leader for these IP developments which are integral parts of Silicon lifecycle monitoring.
You Are:
As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. You will generate test benches and test cases, perform RTL and gate-level SDF-annotated simulations and debug, and may perform mixed-signal (digital + analog) simulations and debug. You will interact with our application engineers and provide guidance to customers. Additionally, you will participate in the generation of data books, application notes, and white papers.
What You’ll Be Doing:
- Generate test benches and test cases.
- Perform RTL and gate-level SDF-annotated simulations and debug.
- May perform mixed-signal (digital + analog) simulations and debug.
- Interact with our application engineers and provide guidance to customers.
- Participate in the generation of data books, application notes, and white papers.
- Perform physical verification and design rule checks to ensure design integrity and manufacturability.
- Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views.
- Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition.
- Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus.
- Knowledge of any high-speed communication protocol is not mandatory but an asset.
- Previous knowledge in customer support and/or silicon bring-up is a plus.
The Impact You Will Have:
- Strengthen and develop forecasting capabilities based on improved monitoring capacity.
- Ensure high-quality and reliable silicon lifecycle monitoring solutions.
- Enhance quality assurance methodology by adding more quality checks/gatings.
- Support internal tools development and automation to improve productivity across ASIC design cycles.
- Work with design engineers on new tools/technology and new features evaluation and adoption.
- Contribute to the successful and smooth operation of the engineering teams.
What You’ll Need:
- Bachelor’s or master’s degree in electrical engineering or a related field.
- 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows.
- Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler.
- Exceptional knowledge of layout design methods, techniques, and methodologies.
- Experience with physical verification tools, such as Calibre or Assura.
- Understanding of semiconductor process technologies and their impact on layout design.
Who You Are:
- Excellent problem-solving and systematic skills.
- Ability to work effectively in a team-oriented environment.
- Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV).
- Good communication and interpersonal skills.
The Team You’ll Be A Part Of:
You will be part of a dynamic team focused on developing cutting-edge PVT Sensor IPs integral to Silicon lifecycle monitoring. This team collaborates closely with other engineering teams to ensure the highest quality and performance of our products.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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