Staff DFT Engineer

Category Engineering Hire Type Employee Job ID 16178 Remote Eligible No Date Posted 06/21/2026

DFT Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years making chips testable, and you know that DFT is not a checkbox at the end of the flow, it is a discipline that shapes architecture decisions from day one. You are the engineer who sees a coverage gap at 98% and does not shrug, you trace it back through the netlist, find the clock domain interaction that everyone missed, and fix it before tapeout.

You are comfortable owning DFT from architecture through sign-off. You have debugged enough pattern simulation failures to know when it is a tool issue, a netlist issue, or a fundamental flaw in the scan strategy, and you can articulate the difference to a design lead in a hallway conversation. You do not wait for someone to tell you what coverage target to hit, you look at the product requirements, the test time budget, and the risk profile, and you make a call.

Working across design, verification, and physical implementation teams does not slow you down, it is how you get the work done. At Synopsys, you will work on IP that powers the semiconductor industry, and the DFT strategies you build will determine whether those designs can be tested at scale.

What You'll Be Doing

• Execute block-level and top-level ATPG, run DRC analysis, and drive coverage optimization to meet product quality and test time targets
• Handle pattern simulations including both timing-aware and non-timing runs, and debug failures down to root cause in the netlist or tool setup
• Develop and implement DFT architectures for IP blocks, including scan insertion strategies, compression schemes, and BIST integration where needed
• Collaborate directly with design, verification, and physical design teams to resolve DFT-related issues and ensure test readiness through the flow
• Own DFT sign-off activities and deliverables for assigned projects, serving as the DFT point of contact from architecture through tapeout
• Define and execute DFT strategies aligned with project schedules, coverage requirements, and manufacturing test constraints
• Debug complex DFT simulation and netlist issues independently, resolving coverage gaps, DRC violations, and pattern failures

The Impact You Will Have

• Your DFT architectures will determine whether complex IP blocks can be tested efficiently at volume production, directly affecting yield and cost
• The coverage optimization work you do will close gaps that would otherwise become field failures or expensive test escapes
• Your collaboration with design and physical teams will catch test issues early, preventing costly respins and schedule slips
• The sign-off rigor you bring will ensure that designs leave Synopsys ready for manufacturing test without surprises
• Your debugging skills will unblock critical path issues that would otherwise delay tapeout schedules
• The DFT strategies you define will scale across multiple projects, setting the standard for test quality and efficiency
• Your ownership of test readiness will give customers confidence that the IP they integrate will work in their test environments

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
• 5+ years of hands-on experience in DFT implementation, including scan insertion, ATPG, and pattern validation
• Strong proficiency with industry-standard DFT tools such as Synopsys TetraMAX, DFT Compiler, or equivalent platforms
• Demonstrated ability to debug complex DFT simulation failures, DRC violations, and coverage issues independently
• Solid understanding of VLSI design flow, including RTL, synthesis, and physical design interactions with DFT
• Experience executing DFT sign-off for block-level or top-level designs in a production environment
• Experience with memory BIST, logic BIST, or advanced compression techniques is a plus

Who You Are

• You can look at a coverage report, spot the outlier that everyone else missed, and trace it back to a scan chain or clock gating issue without needing a week to investigate
• You push back when a design decision will create a test nightmare downstream, and you can explain the tradeoff clearly enough that the design lead actually changes course
• You are organized enough to manage DFT for multiple blocks in parallel without losing track of which one is in pattern validation and which one is waiting on netlist updates
• You do not treat DFT as a solo activity, you pull in the right people from design, verification, and physical teams when you hit a wall, and you make it easy for them to help you
• You know the difference between a DRC violation that is cosmetic and one that will kill coverage, and you triage accordingly
• You take ownership seriously, when you sign off on DFT readiness, it means the design is actually ready, not that you ran out of time to check

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.