Senior Layout Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced Layout Design Engineer with a strong background in Analog Mixed-signal Die to Die IP layout and verification. You possess a deep understanding of high-speed digital layouts and the challenges associated with high-speed signals. With more than 6 years of experience, you have advanced knowledge of deep submicron effects and mitigation strategies, as well as proficiency with advanced tools and floorplanning techniques. Your expertise extends to CMOS and FinFET layouts and process technology, particularly in 28nm and smaller nodes. You have a good grasp of ESD and latchup layout design considerations, and are familiar with the ASIC physical design flow, including LEF generation, Place & Route, and top-level verification flow. You are well-versed in DRC/LVS, LPE, IO frame and pitch requirements, power rail routings, IO abutment rules, bond pad layout, EM and IR considerations, and DFM. Scripting skills for layout automation are a plus. You excel in remote site interaction and layout coordination activities, and you are known for fostering accountability and ownership through hands-on technical leadership. Your excellent written and verbal communication skills enable you to interact effectively with customers and internal development teams.

What You’ll Be Doing:

• Designing high-speed die to die PHY layout.
• Providing subject matter expertise and technical leadership in high-speed design such as Die to Die.
• Collaborating with DDR PHY team, package engineers, and system engineers to meet design specifications.
• Performing scheduling duties and engaging in remote site interactions.
• Supporting critical layout and floorplanning requirements with the local team.
• Coordinating with other layout teams both in Bangalore and globally to detail out layout activities and obtain layout deliverables, including reviewing and quality checking from remote layout teams.
• Ensuring strict flow adherence and policing of internal policies to secure schedules.

The Impact You Will Have:

• Enhancing the quality and performance of high-speed Die to Die layout designs.
• Driving innovation and technical excellence in high-speed design projects.
• Ensuring design specifications are met through effective collaboration with cross-functional teams.
• Maintaining high standards of quality and efficiency in layout deliverables.
• Facilitating seamless coordination and communication with global layout teams.
• Contributing to the success of Synopsys by delivering top-notch layout designs on schedule.

What You’ll Need:

• Experience in Analog Mixed-signal DDR/Serdes/Die to Die IP layout and verification of high-speed digital layout.
• Advanced understanding of deep submicron effects and mitigation strategies.
• Proficiency with advanced tools and floorplanning techniques.
• Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller.
• Good understanding of ESD and latchup layout design considerations.
• Familiarity with ASIC physical design flow: LEF generation, Place & Route, and top-level verification flow, DRC/LVS, LPE.
• Knowledge of IO frame and pitch requirements, power rail routings, IO abutment rules, bondpad layout, EM and IR considerations, DFM, etc.
• Scripting skills for layout automation (a plus).

Who You Are:

• A highly skilled and experienced layout design engineer.
• An effective communicator with excellent written and verbal communication skills.
• A collaborative team player who excels in remote site interaction and layout coordination activities.
• A proactive leader who fosters accountability and ownership through hands-on technical leadership.
• A problem solver with a deep understanding of high-speed digital layouts and high-speed signal challenges.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on designing and developing high-performance silicon chips. Our team collaborates closely with various stakeholders, including DDR PHY team, package engineers, and system engineers, to meet design specifications and deliver top-quality layout designs. We work with layout teams globally, ensuring seamless coordination and communication to achieve our goals.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.