Senior Staff Analog Design Engineer

• Review SerDes standards and architecture documents to develop analog sub-block specifications.
• Identify and refine circuit implementations to achieve optimal power, area and performance targets.
• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
• Oversee physical layout to minimize the effect of parasitic, device stress, and process variation.
• Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
• Present simulation data for peer and customer review.
• Mentor and Review the progress of junior engineers.
• Document design features and test plans.
• Consult on the electrical characterization of your circuit within the SerDes IP product.

• PhD with 5+ years, or MSc with 8+ years of SerDes/High-Speed analog design experience.
• In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
• Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
• Detailed design experience with several of the following SerDes sub-circuits:
  receiver equalizers, data samplers, voltage/current-mode drivers, serializers, de-serializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
• Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
• Direct customer engagements and interaction on high speed PHY such as SERDES, DDR or HBM is a strong plus
• Prior experience on products/test chips bring up, lab debug and simulations to silicon correlation is highly desirable
• Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.)
• Experience with EDA tools for schematic entry, physical layout, and design verification
• Understanding of SPICE simulators and simulation methods
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB
• Ability to provide automation​ for rapid and dynamic design needs is highly sought-after

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.