Senior/Staff ASIC Design Verification Engineer

Category Engineering Hire Type Employee Job ID 15994 Remote Eligible No Date Posted 03/08/2026

Job Descriptions

• Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.
• Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.
• Define, develop, and execute functional verification plans and test strategies.
• Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.
• Generate VCD files and perform power analysis/reporting using PrimeTime PX.

Requirements:

• Minimum of 2 years of experience in ASIC RTL design flow. (Candidates with extensive experience will be considered for senior/lead positions.)
• Proficiency in RTL and GLS verification, with strong debugging capabilities.
• Excellent teamwork and communication skills, with professional proficiency in English.
• Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.