Job Description

The Synopsys Non-Volatile-Memory team is looking for an experienced designer ready to lead the development of our next generation NVM IP. In this role, the candidate will have the opportunity to work on an extremely wide range of process technologies, ranging from complex BCD process nodes to 3nm and beyond. The ideal candidate must be a team player with good written and verbal communication skills, independent and self-motivated, detail oriented, and able to work with a multi-national cross-functional teams.

Responsibilities

• Lead NVM TestChip and IP design flow in multiple technologies and foundries
• Architect/Design/Verify CMOS-based non-volatile memory IP modules
• Collaborate with Product Engineer to perform silicon verification, test and debug to analyze the IP on silicon
• Perform Post layout extraction & simulation, and conduct through testing in conjunction with silicon validation
• Work closely with on/off-site design, layout and CAD teams
•  Collaborate with layout designers on floor planning of memory array and analog blocks
• Be the go-to engineer to support Sales and Application Engineers in complex pre and post-sales customer engagements

Skills and Experience Required

• 15+ years of industry experience in circuit designer, with a strong emphasis on analog circuit design and analysis. Memory design experience is a significant plus.
• Deep understanding of layout considerations for advanced nodes, including parasitic effect, matching techniques and signal integrity
• Expertise in electrical problem-solving, including root cause analysis of circuit failures and the development of effective solutions
• Familiar with TestChip tapeout flow 
• Demonstrated track record of leading successful NVM designs into high volume production 
• Strong transistor level analog design and analysis with sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design
• Good understanding of Non-Volatile Memory design, Memory architecture and device physics 
• Experience circuit debugging capability with analog circuit and various memory blocks 
• Familiar with circuit simulation tools (HSIM, HSPICE, etc.) is required
• Must have prior experience with Custom Complier or equivalent tools (Schematic, and Layout edit)
• Experience with statistical design methodology (generating and analyzing Monte-Carlo results) 
• Hands-on experience of Si debugging (FIB, micro-probing, post layout RC extraction, etc.) 
• Experience with Low power design and power management circuitry
• Experience with FinFET design is a plus