R&D Engineering, Staff Engineer
Overview
Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.
Job Description
Category Engineering Hire Type Employee Job ID 15172 Remote Eligible No Date Posted 02/10/2026
We are seeking a highly skilled Software Engineer to join Zebu timing team in Synopsys.
Synopsys is uniquely positioned to offer the most complete verification solution in market today. ZeBu is the emulation platform of Synopsys verification flow, it’s the industry’s performance & capacity leader in Emulation.
As a Zebu backend R&D, we collaborate with cross-functional teams globally to analyze technical issues, develop the solution for requirements from customer and optimize Zebu QoR everyday.
R&D in timing team needs to learn Static Timing Analysis, timing graph generation and delay estimation techniques. We create a fast and accurate timer to optimize and sign-off runtime frequency in both Zebu and ProtoCompiler.
Requirements:
• Education Requirements
o MS (or above) in Electrical Engineering/Computer Science.
• Skills/Experience
o Good team player and communication skills.
o Good knowledge of proficient in C++, data structure and algorithm.
o B1 or above level English on reading/writing/listening/speaking (especially on discussing and documenting technical spec).
• Nice to have
o Familiar with STA and timer like PrimeTime.
o Familiar with RTL coding , chip design experience or verification env. architect experience,. Understanding ”big picture” at the ASIC architectural and system level with experience on real block/soc verification experience .
o Good expertise on emulators/prototyping like Zebu/Palladium/Veloce/ProtoCompiler/Protium or FPGA compile/runtime/debug are preferred.
o Familiar with FPGA tools likes Xilinx Vivado/Vitis and Synopsys Synplify,
o Familiar with scripting language like Tcl/CSH/BASH/Python/Makefile/Perl.
o Experience on driver/FW FPGA development.
o Familiar with simulation tool like VCS/Verdi
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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