SiCADA Intern - 16432

Hsinchu, Taiwan, Taiwan

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Overview

Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. Explore your interests, share your ideas, and bring them to life while shaping your career path within our inclusive culture that fosters innovation and collaboration. Engineer your future with us!

Job Description

Date posted 03/16/2026

Category Interns/Temp Hire Type Intern Job ID 16432 Remote Eligible No Date Posted 03/16/2026

SiCADA Internship Program 2026

Job Description:
- Assist SiCADA instructor in developing VDM (Verilog Design Methodology) & ADV (Advanced Design Verification) homework specifications.
- Assist in reviewing ADV course materials, including SVTB (SystemVerilog Testbench) and UVM (Universal Verification Methodology), and update the course content.
- Serve as a teaching assistant for the VDM and ADV courses, helping to answer student questions and grade assignments.
- Support SoC implementation course especially STA and UPF teaching assistance if possible.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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As an applicant your resume, skills, and experience are being reviewed for consideration.

Phone Screen

Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role.

Interview

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Offer

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Welcome!

Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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