Principal Analog Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned engineer with a passion for cutting-edge analog design. Your extensive experience with high-speed interfaces, particularly PCIe 6 and PCIe 7 or SerDes PHY designs, positions you as a technical leader in the field. You possess a deep understanding of transistor-level design and have a proven track record of successfully developing high-speed analog building blocks such as LDOs, Bandgap references, ADC/DAC, PLLs, and DLLs. Your expertise in CMOS technologies, including finFET and SOI processes, and your strong background in jitter budgeting analysis make you an invaluable asset to any team. You are adept at collaborating with cross-functional teams, mentoring junior engineers, and ensuring that designs meet stringent performance, power, and area targets. Your ability to oversee the porting of PHY designs to different technology nodes, while maintaining signal integrity and performance, demonstrates your versatility and commitment to excellence.

What You’ll Be Doing:

• Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs.
• Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets.
• Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance.
• Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems.
• Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools.
• Supervise physical layout to minimize parasitics, device stress, and process variation impacts.
• Review simulation and measurement data for design validation and compliance with PCIe standards.
• Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices.
• Document design features, specifications, test plans, and methodologies for future reference.
• Collaborate with the characterization team to validate the electrical performance of circuits in silicon.

The Impact You Will Have:

• Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology.
• Ensure that Synopsys' analog/mixed-signal circuits meet stringent industry standards, enhancing the company's reputation for excellence.
• Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance.
• Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team.
• Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability.
• Enhance the company's design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits.

What You’ll Need:

• PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs.
• Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs.
• Proven silicon experience in developing PHY circuits that meet strict PCIe standards.
• Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design.
• Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis).
• Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity.
• Extensive experience with the porting of PHY designs across different technology nodes.
• Strong expertise in CMOS technologies, including finFET and SOI processes.
• In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking.
• Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration.
• Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes.

Who You Are:

You are a collaborative and innovative problem solver with a keen eye for detail. Your strong communication skills enable you to effectively convey complex technical concepts to both technical and non-technical stakeholders. You are proactive, taking initiative to drive projects forward and overcome challenges. Your passion for continuous learning keeps you at the forefront of technological advancements, and your mentorship helps to cultivate a dynamic and skilled team.

The Team You’ll Be A Part Of:

You will join a highly skilled and dynamic team of engineers dedicated to pushing the boundaries of analog and mixed-signal design. Our team is focused on developing cutting-edge PCIe PHY designs, ensuring that they meet the highest standards of performance and reliability. Collaboration and innovation are at the core of our team's values, and we thrive on solving complex challenges together.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.