This position is hybrid, based in either Nepean or Markham, offering flexibility to work.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated and innovative Staff Digital Design Engineer with a solid understanding of ASIC development flow. You thrive in a dynamic environment and enjoy tackling challenging problems. With 3-6 years of experience in digital design or verification, you are proficient in Verilog and familiar with synthesis and static timing analysis (STA). You have a good grasp of back-end synthesis tools such as DC/FC/PT and a solid understanding of clock domain crossing techniques. Your excellent communication skills enable you to interact effectively with different design groups. You are self-motivated, proactive, and capable of applying good design quality while meeting tight deadlines. Experience in writing micro-architecture specifications, RTL coding and implementation, and defining Clock/Reset domain crossing design constraints is preferred.

What You’ll Be Doing:

- Designing and verifying next-generation digital IP controllers. - Driving innovations in PCIe, UAL, and other cutting-edge technologies. - Collaborating with a highly experienced design and verification team. - Conducting initial training and continuous on-the-job training. - Writing micro-architecture specifications. - RTL coding and implementation. - Defining and evaluating Clock/Reset domain crossing design constraints using CDC/RDC tools.

The Impact You Will Have:

- Contributing to the development of cutting-edge semiconductor solutions. - Enhancing the performance and efficiency of digital IP controllers. - Driving technological advancements in PCIe, UAL, and other key areas. - Supporting the creation of high-performance silicon chips and software content. - Strengthening Synopsys’ leadership in chip design and verification. - Enabling the continuous innovation that shapes the future of technology.

What You’ll Need:

- 3-6 years of digital design or verification experience. - Proficiency in Verilog. - Familiarity with synthesis and static timing analysis (STA). - Good knowledge of back-end synthesis tools (DC/FC/PT). - Solid understanding of clock domain crossing techniques.

Who You Are:

- Self-motivated and proactive. - Able to apply good design quality while meeting tight deadlines. - Excellent communicator, capable of interacting with different design groups. - Innovative and eager to tackle challenging problems. - Detail-oriented and committed to continuous learning and improvement.

The Team You’ll Be A Part Of:

You will be part of a highly experienced design and verification team focused on developing next-generation digital IP controllers. The team is dedicated to driving innovations in key technologies such as PCIe and UAL, contributing to the development of cutting-edge semiconductor solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.