ASIC Digital Design, Sr Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.
Key Qualifications
- BSEE or MSEE plus a minimum of 2 years of digital design and/or verification experience in the industry
- Must be familiar with Verilog and VCS.
- Good knowledge and working experience of synthesis tools DC/FC and PT is required
- Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
- Good Knowledge and Experience in Spyglass/VC-Spyglass.
- Experience in Core Assembler flow to create, verify and use Core Kit views for IPs
- Scripting experience in Shell/Perl/Python/TCL is a strong plus.
- Good communication skills for interacting between different design groups and customer support teams are required.
- Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines
- Resolves issues in creative ways and exercises independent judgment in selecting methods and techniques to obtain solutions
- May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise
- Must exhibit ability to produce good results as an individual and team contributor
- Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
- Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
- Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols
- Creating, verifying and using Core-Kit views in Core Assembler flow.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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