ASIC Digital Design, Sr Manager-13488

Category Engineering Hire Type Employee Job ID 13488 Base Salary Range $204000-$306000 Remote Eligible Yes Date Posted 03/12/2025

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams—architecture, verification, physical implementation, and firmware—to deliver industry-leading DDR PHY IP solutions.

Your leadership style is empowering, fostering growth and development within your team, and you’re committed to cultivating a culture of technical excellence, accountability, and innovation. You bring strategic thinking to every challenge, balancing performance, timing, and power targets while adapting to evolving customer needs. Excellent communication skills and a self-driven attitude make you a trusted mentor and partner, both internally and with customers integrating cutting-edge IP into their SoCs. If you’re excited to shape the future of high-bandwidth, low-latency silicon IP, Synopsys is the place for you.

What You’ll Be Doing:

• Leading a diverse team of design engineers in the development of next-generation DDR PHY IP solutions.
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Driving all phases of DDR PHY IP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth and a culture of innovation.
• Engaging with customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

The Impact You Will Have:

• Delivering industry-leading DDR PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency.
• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
• Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
• Enhancing product quality and reliability through rigorous design and verification processes.
• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

What You’ll Need:

• Bachelor’s degree or higher in Electrical Engineering, with 12-15 years of complex technical development experience.
• Minimum 2 years’ experience in people management and employee development.
• Proficiency in synthesizable Verilog and SystemVerilog design concepts and implementation.
• Strong background in front-end design flows: linting, synthesis, static timing analysis (STA), cross-domain clocking, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding of DDR memory and DDR PHY architecture is a plus.

Who You Are:

• Inspirational leader who motivates and develops technical talent.
• Strong problem-solver with a strategic, analytical mindset.
• Collaborative team player who excels in cross-functional environments.
• Effective communicator who can translate complex technical concepts to diverse audiences.
• Self-starter who thrives in a fast-paced, innovative setting.

The Team You’ll Be A Part Of:

You’ll join the Synopsys DDR PHY IP team—a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.