Senior Applications Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an enthusiastic engineer with a passion for digital design and EDA technologies, eager to advance your expertise in timing constraints and automation. You thrive in collaborative environments, working across diverse teams to bridge design intent and implementation. Your foundation in digital circuit concepts and static timing analysis (STA) gives you the confidence to tackle complex constraint issues, and your curiosity drives you to explore advanced methodologies and scripting solutions. You are meticulous in your approach, ensuring every constraint is validated and documented, and you value clear communication to foster alignment across RTL, physical design, and CAD teams. You embrace challenges as opportunities to learn, adapt, and innovate, and you are committed to helping customers achieve successful timing closure in their ASIC and SoC projects. Your analytical mindset, coupled with your ability to translate technical concepts into actionable insights, makes you a trusted resource for teams navigating the intricacies of timing constraints management. With a growth-oriented attitude, you seek mentorship and knowledge-sharing, contributing both as a learner and as a leader in best practices. You believe in the power of automation to streamline workflows and are excited to work with industry-leading Synopsys tools to solve real-world design challenges.

What You’ll Be Doing:

• Assisting in the creation, validation, and maintenance of timing constraints (SDC) using Synopsys Timing Constraints Manager (TCM).
• Supporting constraint development for clocks, I/O interfaces, generated clocks, false paths, multicycle paths, and clock domain crossings (CDC).
• Identifying and resolving constraint-related issues impacting static timing analysis (STA) and signoff, ensuring design quality and reliability.
• Providing technical support and enablement for Synopsys EDA tools including PrimeTime, Design Compiler, Fusion Compiler, and TCM.
• Collaborating withSynopsyscustomerscompaniesindigital design, physical implementation, and CAD to debug timing and constraint issues and align constraints with design intent.
• Developing scripts (Python, Tcl, Perl) and dashboards to analyze timing constraints, automate workflows, and track constraint quality and timing health.
• Documenting methodologies, workflows, and guidelines for effective timing constraints management.

The Impact You Will Have:

• Enhance timing closure workflows for complex ASIC and SoC projects, improving overall design quality and performance.
• EmpowerSynopsys customers anddesign teams with accurate and robust timing constraints, reducing signoff risks and accelerating project timelines.
• Drive best practices in constraint authoring and verification, contributing to industry-leading methodologies.
• Enable cross-functional teams to achieve seamless collaboration and alignment on timing requirements.

• Advance automation and efficiency in timing analysis through innovative scripting and dashboard solutions.
• Provide critical technical support to customers, ensuring successful adoption and utilization of Synopsys tools.

What You’ll Need:

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Solid understanding of digital design fundamentals and synchronous circuit design.
• Basic knowledge of static timing analysis (STA) concepts: setup/hold, slack, timing paths, clock trees, etc.
• Familiarity with Synopsys EDA tools (PrimeTime, Design Compiler, ICC2/Fusion Compiler) or similar industry tools.
• Experience with scripting languages such as Tcl and/or Python for automation and analysis.
• Exposure to Synopsys Timing Constraints Manager (TCM) and SDC constraints is preferred.
• Knowledge of ASIC/SoC design flow, physical design concepts, CDC/RDC, low-power design (UPF/CPF), or multi-mode multi-corner (MMMC) analysis is a plus.
• Experience working in Linux/Unix environments.

Who You Are:

• Analytical and detail-oriented, with strong problem-solving skills.
• Clear communicator, able to explain technical concepts to cross-functional teams.
• Collaborative team player, fostering effective partnerships across disciplines.
• Adaptable and eager to learn new tools, technologies, and methodologies.
• Organized and diligent in documentation, ensuring repeatable and scalable workflows.
• Proactive in seeking mentorship, feedback, and continuous improvement.