Design Verification, Principal Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly experienced Verification Engineer with a robust background in architecting verification environments for complex serial protocols. With a BSEE in Electrical Engineering and 18+ years of relevant experience or an MSEE with 14+ years of relevant experience, you excel in developing HVL (System Verilog) based test environments and implementing test plans. Your exceptional HVL coding skills and hands-on experience with industry-standard simulators such as VCS, NC, MTI, and waveform-based debugging tools set you apart. You are proficient in verification methodologies such as VMM/OVM/UVM and have exposure to Formal verification methodologies. Your knowledge of protocols like HBM, DDR, or LPDDR, along with familiarity with HDLs such as Verilog and scripting languages like Perl, TCL, and Python, make you an ideal candidate. You possess excellent written and oral communication skills, demonstrate strong testing, debugging, and problem-solving abilities, and show high levels of initiative.

What You’ll Be Doing:

- Specifying, designing/architecting, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores. - Performing verification tasks for IP cores and working closely with RTL designers. - Engaging in test planning, test environment coding at both unit and system levels, and test case coding. - Debugging and managing functional coverage coding and testing, meeting quality metric goals, and managing regression. - Collaborating with a global team of professional verification engineers. - Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

The Impact You Will Have:

- Enhancing the reliability and performance of Synopsys' IP cores through meticulous verification processes. - Contributing to the development of cutting-edge connectivity protocols that power a wide range of applications. - Ensuring high-quality and robust verification environments that support the DesignWare family of synthesizable cores. - Driving innovation in verification methodologies and techniques within the team. - Supporting the continuous improvement of verification metrics and quality standards. - Playing a key role in the success of Synopsys' IP design and verification processes.

What You’ll Need:

- BSEE in Electrical Engineering with 18+ years of relevant experience or MSEE with 14+ years of relevant experience. - Experience in architecting verification environments for complex serial protocols. - Proficiency in developing HVL (System Verilog) based test environments and implementing test plans. - Exceptional HVL coding skills and hands-on experience with industry-standard simulators and waveform-based debugging tools. - Proficiency in verification methodologies such as VMM/OVM/UVM. - Knowledge of protocols like HBM, DDR, or LPDDR and familiarity with HDLs and scripting languages.

Who You Are:

- A detail-oriented professional with excellent problem-solving and debugging skills. - A proactive individual who shows high levels of initiative and can work independently. - A strong communicator with good written and oral communication skills. - A collaborative team player who works well in a global team environment. - A continuous learner who stays updated with the latest verification methodologies and technologies.

The Team You’ll Be A Part Of:

You will be part of the DesignWare HBM IP Verification R&D team at Synopsys, working closely with RTL designers and a global team of professional verification engineers. The team focuses on developing state-of-the-art verification environments for the DesignWare family of synthesizable cores and working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.