ASIC Physical Design Senior Engineer

Category Engineering Hire Type Employee Job ID 17357 Remote Eligible No Date Posted 05/12/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent your career turning netlists into silicon that actually works, and you know that the gap between a clean synthesis output and a chip that meets timing, power, and area targets is where the real engineering happens. Floorplanning is not just dropping blocks on a canvas for you, it is understanding congestion before it becomes a routing nightmare three weeks later.

You are comfortable living in Fusion Compiler or ICCII for days at a time, running iterations, tweaking constraints, and watching slack numbers move in the right direction. When a signoff tool flags a violation, you do not panic or guess. You dig into the root cause, whether it is a clock tree imbalance, an IR drop hotspot, or a DRC you inherited from floorplan. Scripting is not a nice-to-have for you, it is how you stay sane. You write Python or Tcl to automate the repetitive parts so you can focus on the decisions that actually matter.

What You'll Be Doing

• Take designs from netlist to GDSII, owning the full physical implementation flow for PHY, test chip, and subsystem-level blocks
• Build and optimize floorplans, including power grid planning, pin placement, and macro positioning that set up the rest of the flow for success
• Run placement, clock tree synthesis, and post-CTS optimization to meet timing, power, area, congestion, and signal integrity targets
• Perform signoff-level timing analysis using PrimeTime, close EMIR violations, and drive physical verification clean using ICV
• Execute ECOs to resolve timing, power, or physical verification issues without destabilizing the design
• Write and maintain Python, Tcl, Perl, or bash automation scripts to improve flow efficiency and reduce manual intervention

The Impact You Will Have

• Your floorplans and implementation decisions will directly determine whether designs meet their PPA targets and tape out on schedule
• Signoff-quality closure work you deliver will reduce respin risk and get silicon into production faster
• Automation scripts you build will be reused across multiple projects, saving engineering hours and improving consistency
• Your ability to debug and resolve complex timing, power, and physical verification issues will unblock critical project milestones
• The designs you implement will power real products used by Synopsys customers across the semiconductor industry

What You'll Need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• Hands-on experience in ASIC physical design and implementation, taking designs through the full RTL to GDSII flow
• Proficiency with Synopsys Fusion Compiler, ICC II, PrimeTime, and ICV, or equivalent industry-standard tools
• Solid understanding of static timing analysis, including setup/hold closure, clock tree balancing, and multi-corner multi-mode constraints
• Working knowledge of EMIR analysis and physical verification, including DRC, LVS, and antenna checks
• Scripting ability in Python, Tcl, Perl, or bash, with experience using makefiles and version control systems like Git

Who You Are

• You can look at a floorplan and spot congestion risks or timing bottlenecks before you even start placement
• When a signoff tool throws a violation, you trace it back to the root cause and prevent it from happening again
• You are comfortable working with incomplete or evolving constraints, asking the right questions to fill in gaps without stalling progress
• You can explain a complex timing path or power grid issue to a colleague in a way that makes sense, without drowning them in jargon

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.