Layout Design, Staff Engineer

Category Engineering Hire Type Employee Job ID 17463 Remote Eligible No Date Posted 05/24/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years translating circuit intent into physical reality, and you know that a layout is not just geometry, it is a series of decisions that either enable performance or quietly kill it. The difference between a chip that meets spec and one that does not often comes down to a placement choice, a routing strategy, or a guard ring you added because you have seen what happens when you skip it.

You do not wait for someone to tell you the layout is wrong. You catch it during floorplanning, during routing, during the third DRC iteration when everyone else is ready to tape out. You have debugged LVS mismatches at 11 p.m. before a milestone and found the issue because you know how to read a schematic against a layout and spot what does not belong. Working across circuit design, verification, and manufacturing teams does not intimidate you. You ask the right questions, push back when a constraint does not make sense, and find solutions that work without compromising the design.

What You'll Be Doing

• Design and develop custom layout for complex analog, mixed-signal, or digital blocks, ensuring compliance with design rules, performance targets, and manufacturability constraints
• Perform physical verification including DRC, LVS, and PERC, resolving violations and working with process teams to close out tape-out readiness
• Collaborate directly with circuit designers to optimize layout for power, performance, area, and reliability
• Own layout deliverables for entire subsystems or critical IP blocks, managing timelines and coordinating with verification and project teams to meet tape-out schedules
• Participate in design reviews, identify layout risks early, and propose solutions that balance technical tradeoffs
• Drive process improvements within the layout team, including automation scripts, design methodology updates, and best practice documentation

The Impact You Will Have

• Your layout decisions will directly influence the performance, yield, and manufacturability of semiconductor products used in high-performance computing and AI
• Designs you deliver will tape out on time and meet stringent power, area, and reliability specifications
• Physical verification work you complete will reduce costly respins and catch issues before they reach the fab
• Collaboration with circuit and verification teams will result in optimized layouts that meet both electrical and physical constraints without unnecessary iteration
• Process improvements and automation you contribute will increase layout efficiency and quality across the team
• Your ownership of complex layout blocks will enable the broader design team to focus on innovation

What You'll Need

• Bachelor's degree in Electrical Engineering, Electronics, or a related field, advanced degree is a plus
• 5+ years of hands-on experience in custom IC layout design, with demonstrated ability to deliver complex layouts through tape-out
• Strong proficiency with industry-standard layout tools such as Cadence Virtuoso, Mentor Calibre, or equivalent platforms
• Deep understanding of semiconductor manufacturing processes, design rules, and tape-out requirements including DRC, LVS, and parasitic extraction
• Proven ability to resolve complex layout issues related to performance, reliability, or manufacturability
• Experience working cross-functionally with circuit designers, verification engineers, and project managers

Who You Are

• You can look at a schematic and a floorplan and immediately start thinking about routing strategy, device matching, and where the noise is going to come from
• When a DRC violation shows up in a critical path two days before tape-out, you isolate it, understand the root cause, and fix it without breaking something else
• You push back when a circuit designer asks for something that will hurt yield or performance, and you do it with enough technical clarity that they understand the tradeoff
• You stay organized across multiple layout blocks, verification runs, and project timelines without letting details slip

The Team You'll Be Part Of

You will be part of a dynamic and diverse engineering team at Synopsys Armenia, where collaboration, continuous learning, and creative problem solving drive the development of layout solutions for leading semiconductor products. The team works to advance the boundaries of chip design and technology, and you will contribute to projects that help shape the future of high-performance integrated circuits while working with talented professionals around the world.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.